= Usiii =


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== Infobox BSP ==
||'''BSP_name'''     ||usiii||
||'''Manufacturer''' ||Sun Microsystems||
||'''image'''        ||||
||'''caption'''      ||||
||'''Board_URL'''    ||[http://datasheets.chipdb.org/Sun/UltraSparc-IIIi.pdf]||
||'''Architecture''' ||SPARC-V9||
||'''CPU_model '''   ||sun4u||
||'''Monitor '''     ||||
||'''Simulator'''    ||Yes. Simics||
||'''Aliases '''     ||||
||'''RAM '''         ||DDR SDRAM (128b data, 9b ECC 80-122 MHz),L1 Cache: on-chip 64 KB (data), 32 KB (instruction) ,L2 Cache: on-chip 1 MB (4-way, set-associative) ||
||'''NVMEM'''        ||||
||'''Serial'''       ||||
||'''NICs'''         ||||
||'''Other'''        ||Memory size, 16GB per CPU,Bus Bandwidth, 4.25 GB/s (peak)||

= Overview =


Describe the board here.  Include links to manuals, brochures, etc.

UltraSPARC III is a 64-bit SPARC processor conforming to the original SPARC v9, referred to as sun4u.

This BSP is in development, and is currently in "beta" stage. Original sources are available from the [http://code.google.com/p/rtemssparc64/ rtemssparc64] Google Code repository. The development directory is rtems/rtemscvs. This BSP is merged in the RTEMS 4.11 development series.
= Manuals =

[http://developers.sun.com/solaris/articles/sparcv9.html The SPARC Architecture Manual, Version 9]

[http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.22.6228&rep=rep1&type=pdf UltraSPARC User's Manual]

[http://datasheets.chipdb.org/Sun/UltraSparc-IIIi.pdf UltraSPARC IIIi Processor]

[http://developers.sun.com/solaris/articles/sparcv9abi.html Register ABI Compliance]
= Board Setup =


If there are special jumper or ROM monitor settings, describe them.
= Downloading and Executing =


Describe the download procedure.
= Simulators =

Development of this BSP has been exclusively on simulators. There is no current documentation for using this BSP with real hardware.
= Simics =

Simics is a commercially licensed simulator.  These instructions assume you can set up and run Simics independently and have the proper licenses.  For a free simulator, try M5 as described below.

Follow the instructions provided with Simics for the Niagara target. You will need to download and extract the [http://www.opensparc.net/offers/OpenSPARCT1_Arch.1.5.tar.bz2 OpenSparc architecture and performance modeling tools].

Bundle RTEMS executables and SILO on to a bootable ISO9660 filesystem.  [http://code.google.com/p/rtemssparc64/ rtemssparc64] has some scripts to help create the bootable disk.  More details on how to do this will be forthcoming.
= Debugging =


This BSP is debugged using Simics.  M5 full system simulation supports using GDB as a remote debugger, but it has not been successfully used with RTEMS yet.

=Test Reports=



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