Changes between Version 3 and Version 4 of TBR/BSP/Usiii


Ignore:
Timestamp:
Nov 8, 2018, 5:54:59 PM (7 months ago)
Author:
Pritish Jain
Comment:

Fixed Infobox

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  • TBR/BSP/Usiii

    v3 v4  
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    11 {{Infobox BSP
    12 |BSP_name     = usiii
    13 |Manufacturer = Sun Microsystems
    14 |image        =
    15 |caption      =
    16 |Board_URL    = http://datasheets.chipdb.org/Sun/UltraSparc-IIIi.pdf
    17 |Architecture = SPARC-V9
    18 |CPU_model    = sun4u
    19 |Monitor      =
    20 |Simulator    = Yes. Simics
    21 |Aliases      =
    22 |RAM          = DDR SDRAM (128b data, 9b ECC 80-122 MHz)
    23 L1 Cache: on-chip 64 KB (data), 32 KB (instruction)
    24 L2 Cache: on-chip 1 MB (4-way, set-associative)
    25 |NVMEM        =
    26 |Serial       =
    27 |NICs         =
    28 |Other        = Memory size, 16GB per CPU
    29 Bus Bandwidth, 4.25 GB/s (peak)
    30 }}
     11== Infobox BSP ==
     12||'''BSP_name'''     ||usiii||
     13||'''Manufacturer''' ||Sun Microsystems||
     14||'''image'''        ||||
     15||'''caption'''      ||||
     16||'''Board_URL'''    ||[http://datasheets.chipdb.org/Sun/UltraSparc-IIIi.pdf]||
     17||'''Architecture''' ||SPARC-V9||
     18||'''CPU_model '''   ||sun4u||
     19||'''Monitor '''     ||||
     20||'''Simulator'''    ||Yes. Simics||
     21||'''Aliases '''     ||||
     22||'''RAM '''         ||DDR SDRAM (128b data, 9b ECC 80-122 MHz),L1 Cache: on-chip 64 KB (data), 32 KB (instruction) ,L2 Cache: on-chip 1 MB (4-way, set-associative) ||
     23||'''NVMEM'''        ||||
     24||'''Serial'''       ||||
     25||'''NICs'''         ||||
     26||'''Other'''        ||Memory size, 16GB per CPU,Bus Bandwidth, 4.25 GB/s (peak)||
     27
    3128= Overview =
    3229