Infobox BSP

BSP_name usiii
Manufacturer Sun Microsystems
Architecture SPARC-V9
CPU_model sun4u
Simulator Yes. Simics
RAM DDR SDRAM (128b data, 9b ECC 80-122 MHz),L1 Cache: on-chip 64 KB (data), 32 KB (instruction) ,L2 Cache: on-chip 1 MB (4-way, set-associative)
Other Memory size, 16GB per CPU,Bus Bandwidth, 4.25 GB/s (peak)


Describe the board here. Include links to manuals, brochures, etc.

UltraSPARC III is a 64-bit SPARC processor conforming to the original SPARC v9, referred to as sun4u.

This BSP is in development, and is currently in "beta" stage. Original sources are available from the rtemssparc64 Google Code repository. The development directory is rtems/rtemscvs. This BSP is merged in the RTEMS 4.11 development series.


The SPARC Architecture Manual, Version 9

UltraSPARC User's Manual

UltraSPARC IIIi Processor

Register ABI Compliance

Board Setup

If there are special jumper or ROM monitor settings, describe them.

Downloading and Executing

Describe the download procedure.


Development of this BSP has been exclusively on simulators. There is no current documentation for using this BSP with real hardware.


Simics is a commercially licensed simulator. These instructions assume you can set up and run Simics independently and have the proper licenses. For a free simulator, try M5 as described below.

Follow the instructions provided with Simics for the Niagara target. You will need to download and extract the OpenSparc architecture and performance modeling tools.

Bundle RTEMS executables and SILO on to a bootable ISO9660 filesystem. rtemssparc64 has some scripts to help create the bootable disk. More details on how to do this will be forthcoming.


This BSP is debugged using Simics. M5 full system simulation supports using GDB as a remote debugger, but it has not been successfully used with RTEMS yet.

=Test Reports=


Last modified on Nov 9, 2018 at 7:53:29 AM Last modified on Nov 9, 2018, 7:53:29 AM