| 3 | ||BSP Information |
| 4 | ||BSP_name || TMS570 (TMS570LS3137 HDK) |
| 5 | ||Manufacturer || Texas Instruments |
| 6 | ||image || TMS570LS31x_HDK_Kit.jpg |
| 7 | ||caption || TMS570LS31x HDK Kit |
| 8 | ||Board_URL || http://www.ti.com/tool/tmds570ls31hdk |
| 9 | ||Architecture || ARM Cortex-R (big-endian) |
| 10 | ||CPU_model || Texas Instruments Cortex-R TMS570LS3137 microcontroller |
| 11 | ||Monitor || None, simple HW setup or XCP loader |
| 12 | ||Simulator || No. |
| 13 | ||Aliases || tms570ls3137_hdk, tms570ls3137_hdk_intram, tms570ls3137_hdk_sdram |
| 14 | ||RAM || 256 kB ECC SRAM internal + 8 MB SDRAM |
| 15 | ||NVMEM || 3 MB ECC Flash |
| 16 | ||Serial || 2 x UARTs (1 with LIN), 1 x I2C, 3 x CAN, 1 x 2ch FlexRay, 3+2 x SPI |
| 17 | ||NICs || 1 x 10/100 Ethernet |
| 18 | ||Dimensions || 125 x 110 mm |
| 19 | ||Other || 2 x N2HET timing coprocessor, 2 x ADC |
4 | | {{Infobox BSP |
5 | | |BSP_name = TMS570 |
6 | | |Manufacturer = Texas Instruments |
7 | | |image = TMS570LS31x_HDK_Kit.jpg |
8 | | |caption = TMS570LS31x HDK Kit |
9 | | |Board_URL = http://www.ti.com/tool/tmds570ls31hdk |
10 | | |Dimensions = 125 x 110 mm |
11 | | |Architecture = ARM Cortex-R (big-endian) |
12 | | |CPU_model = Texas Instruments Cortex-R TMS570LS3137 microcontroller |
13 | | |Power = Powered by included adapter |
14 | | |Aliases = None |
15 | | |RAM = 256 kB ECC SRAM internal + 8 MB SDRAM |
16 | | |NVMEM = 3 MB ECC Flash |
17 | | |Serial = 1 x I2C, 3 x CAN, 1 x 2ch FlexRay, 2 x UARTs (1 with LIN), 3+2 x SPI |
18 | | |NICs = 10/100 Ethernet |
19 | | |Other = 2 x N2HET timing coprocessor, 2 x ADC |
20 | | }} |
21 | | = Warning = |
| 21 | = Overview = |
26 | | The TMS570 support has been included in RTEMS mainline sources ([http://git.rtems.org/rtems/commit/?id=4407ee675cb22e8bb870a76eafc590eb6e754315 commit]). |
| 27 | * Texas Instruments TMS570LS3137 MCU: |
| 28 | * Dual CPUs in lockstep |
| 29 | * CPU and memory Built-In Self-Test (BIST) logic |
| 30 | * ECC on both the flash and the data SRAM |
| 31 | * Parity on peripheral memories |
| 32 | * Loopback capability on peripheral I/Os |
| 33 | |
| 34 | = BSP Status = |
| 35 | |
| 36 | The basic TMS570 support has been included in RTEMS mainline sources ([http://git.rtems.org/rtems/commit/?id=4407ee675cb22e8bb870a76eafc590eb6e754315 commit]) in August 2014. Support for initial hardware setup and basic system selftest has been included in RTEMS mainline in September 2016 ([https://git.rtems.org/rtems/commit/?id=29430a3a106c98d2027b29d074d5db85ddb49c39 commit]) |
| 37 | |
| 38 | Development of the BSP started as Premysl Houdek's GSoC 2014 project at [http://industrialinformatics.cz/ Industrial Informatics group of Czech Technical University in Prague] |
116 | | The hello world, ticker and most of the other tests are running from internal SRAM. There are some |
117 | | issues for some of the tests when run from SDRAM. Running of test from Flash has been tested |
118 | | as well. Tests has been linked to offset start address in this case to left setup code to run |
119 | | before tests from Flash start. |
| 123 | The hello world, ticker and most of the other tests are running from internal SRAM, Flash and external SDRAM. Loader or other HW configuration is required to run code from external SDRAM. Running from Flash with complete hardware initialization included in RTEMS application image requires to configure RTEMS BSP build with TMS570_USE_HWINIT_STARTUP option set to 1. |
| 124 | |
| 125 | {{{ |
| 126 | TMS570_USE_HWINIT_STARTUP=1 |
| 127 | }}} |
| 128 | |