wiki:TBR/BSP/SPARC_Instruction_Simulator_(sis)

Version 4 (modified by C Rempel, on Jan 4, 2013 at 6:59:23 AM) (diff)

Completed by A. Long as part of Google Code In 2012

SPARC Instruction Simulator (sis)

{{Infobox BSP

|BSP_name = SPARC Instruction Simulator (sis)

|Manufacturer = ESTEC

|Architecture = SPARC V7

|image =

|Board_URL = http://www.esa.int/TEC/Software_engineering_and_standardisation/TECS2BUXBQE_0.html

|CPU_model = ERC32

|Simulator = SPARC Instruction Simulator

|NVMEM = 16 MB ROM

|RAM = 32 MB

|Video =

}}

This is a variant of the Erc32 BSP which runs on the SPARC ERC32 Simulator (SIS) in gdb. It has special code enabled which is required on the simulator but not on real hardware.

NOTE: Prior to October 2005, this variant did not exist. As a compromise between users who wanted all code not needed on fielded Erc32 hardware and those who wanted RTEMS to continue to run on the simulator built into gdb, this variant was created.

Test Reports

4.7-branch 2006-11-16: User:JoelSherrill? reports that all tests appear to run successfully.