Changes between Version 3 and Version 4 of TBR/BSP/SPARC_Instruction_Simulator_(sis)


Ignore:
Timestamp:
Jan 4, 2013, 6:59:23 AM (7 years ago)
Author:
C Rempel
Comment:

Completed by A. Long as part of Google Code In 2012

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  • TBR/BSP/SPARC_Instruction_Simulator_(sis)

    v3 v4  
    11= SPARC Instruction Simulator (sis) =
    22
     3
     4{{Infobox BSP
     5
     6|BSP_name     = SPARC Instruction Simulator (sis)
     7
     8|Manufacturer = ESTEC
     9
     10|Architecture = SPARC V7
     11
     12|image        =
     13
     14|Board_URL    = http://www.esa.int/TEC/Software_engineering_and_standardisation/TECS2BUXBQE_0.html
     15
     16|CPU_model    = ERC32
     17
     18|Simulator    = SPARC Instruction Simulator
     19
     20|NVMEM        = 16 MB ROM
     21
     22|RAM          = 32 MB
     23
     24|Video        =
     25
     26}}
    327
    428This is a variant of the [wiki:TBR/BSP/Erc32 Erc32] BSP which runs on the SPARC ERC32 Simulator (SIS) in gdb.  It has special code enabled which is required on the simulator but not on real hardware.