Changes between Version 8 and Version 9 of TBR/BSP/SPARC_Instruction_Simulator_(sis)


Ignore:
Timestamp:
Nov 7, 2018, 8:11:10 AM (6 months ago)
Author:
Mehr Mohammad Sachal
Comment:

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  • TBR/BSP/SPARC_Instruction_Simulator_(sis)

    v8 v9  
    33'''NOTE:''' This BSP is obsolete in RTEMS 5.1. The erc32 BSP can be used directly with sparc-rtems5-gdb.
    44
    5 {{Infobox BSP
     5= BSP INFOBOX =
     6||'''BSP_name'''||SPARC Instruction Simulator (sis)||
     7||'''Manufacturer'''||ESTEC||
     8||'''Architecture'''||SPARC V7||
     9||'''image'''||-||
     10||'''Board_URL'''||http://www.esa.int/TEC/Software_engineering_and_standardisation/TECS2BUXBQE_0.html||
     11||'''CPU_model'''||ERC32||
     12||'''Simulator'''||SPARC Instruction Simulator||
     13||'''NVMEM'''||16 MB ROM||
     14||'''RAM'''||32 MB||
     15||'''Video'''||-||
    616
    7 |BSP_name     = SPARC Instruction Simulator (sis)
    8 
    9 |Manufacturer = ESTEC
    10 
    11 |Architecture = SPARC V7
    12 
    13 |image        =
    14 
    15 |Board_URL    = http://www.esa.int/TEC/Software_engineering_and_standardisation/TECS2BUXBQE_0.html
    16 
    17 |CPU_model    = ERC32
    18 
    19 |Simulator    = SPARC Instruction Simulator
    20 
    21 |NVMEM        = 16 MB ROM
    22 
    23 |RAM          = 32 MB
    24 
    25 |Video        =
    26 
    27 }}
    2817
    2918This is a variant of the [wiki:TBR/BSP/Erc32 Erc32] BSP which runs on the SPARC ERC32 Simulator (SIS) in gdb.  It has special code enabled which is required on the simulator but not on real hardware.