wiki:TBR/BSP/SPARC_Instruction_Simulator_(sis)

SPARC Instruction Simulator (sis)

NOTE: This BSP is obsolete in RTEMS 5.1. The erc32 BSP can be used directly with sparc-rtems5-gdb.

BSP INFOBOX

BSP_nameSPARC Instruction Simulator (sis)
ManufacturerESTEC
ArchitectureSPARC V7
image-
Board_URLhttp://www.esa.int/TEC/Software_engineering_and_standardisation/TECS2BUXBQE_0.html
CPU_modelERC32
SimulatorSPARC Instruction Simulator
NVMEM16 MB ROM
RAM32 MB
Video-

This is a variant of the Erc32 BSP which runs on the SPARC ERC32 Simulator (SIS) in gdb. It has special code enabled which is required on the simulator but not on real hardware.

NOTE: Prior to October 2005, this variant did not exist. As a compromise between users who wanted all code not needed on fielded Erc32 hardware and those who wanted RTEMS to continue to run on the simulator built into gdb, this variant was created. This BSP variant was obsoleted in October 2016 (applicable to RTEMS 5+) because the erc32 BSP now works correctly on the gdb simulator.

Test Reports

4.7-branch 2006-11-16: User:JoelSherrill? reports that all tests appear to run successfully.

Last modified on Nov 7, 2018 at 8:11:10 AM Last modified on Nov 7, 2018, 8:11:10 AM