Version 22 (modified by JoelSherrill, on 11/13/11 at 06:30:25) (diff)

Add info on how to obtain this BSP


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{{Infobox BSP |BSP_name = RAD750 |Manufacturer = BAE |image = Bae cimg eis rad750 family.jpg |caption = RAD750 3U, CPU, and 6U |Board_URL = |Architecture = PowerPC |CPU_model = RAD750 |Monitor = SUROM |Simulator = None freely available |Aliases = rad750_3u, rad750_6u, rad750_3u_debug, and rad750_6u_debug BSP |RAM = 128 MB |NVMEM = XX KB EEPROM |Serial = one. NS16550 compatible |NICs = None |Video = None |Other = Radiation Hardened }}

This BSP is under export restrictions and thus cannot be included in the normal public RTEMS distributions. Please contact |OAR Corporation for details on how to obtain this BSP.


The BAE Systems RAD750 Single Board Computer contains a RAD750 PowerPC cpu and a Power PCI intelligent bridge with peripherals. This bsp uses a large amount of shared functionality since this cpu is a hardened version of the the PowerPC 750, the Power PCI contains a ns16550 compatible UART, and the Power PCI appears to be PReP compliant. At this time there are four supported configurations across two boards to allow building for 3U or 6U in production and debug configurations. The debug configurations are built with options which make it possible to debug using the Corelis JTAG emulator. The following lists the BSP variants:

  • rad750_3u - 3U board, production build
  • rad750_6u - 6U board, production build
  • rad750_3u_debug - 3U board, debug build
  • rad750_6u_debug - 6U board, debug build

The configuration settings for the BSP variants are as follows:

The following constants are the same for all configurations:


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|BSP Variant | rad750_3u | rad750_3u_debug | rad750_6u | rad750_6u_debug
defined undefined 0 1 1 1 0
defined undefined 1 0 0 0 1
undefined defined 0 1 1 1 0
undefined defined 1 0 0 0 1


The constants are defined as follows:

  • BSP_DIRTY_MEMORY - When set to 1, the BSP Framework will put a non-zero pattern into the RTEMS Workspace and C program heap.
  • BSP_PRESS_KEY_FOR_RESET - When set to 1, the application will print a message and wait until pressed before resetting board when application exits
  • CONSOLE_USE_INTERRUPTS - When set to 1, the console operates in interrupt mode. Otherwise, it operates in polled mode.
  • ENHANCED_PPCI - When set to 1, the Ehanced PPCI chip is selected.
  • ENABLE_SHADOWED_DATA - When set to 1, a shadow copy of initialized data is made on the first run and is reloaded on subsequent runs.
  • BSP_RESET_BOARD_AT_EXIT - When set to 1, the board will be reset when the application exits.
  • PPC_USE_DATA_CACHE - When set to 1, Data cache is enabled
  • PPC_USE_INSTRUCTION_CACHE - When set to 1, instruction cache is enabled
  • SHOW_PCI_SETTING - When set to 1, the PCI bus and slot findings are displayed during startup

Board Setup

If there are special jumper or ROM monitor settings, describe them.

Downloading and Executing

Describe the download procedure.


How do you debug code on this board? What gdb setup? BDM, stub, etc?

Test Reports

{{Test Report |Version = CVS head |Date = DATE |User = User:WhoTestedThis? |Report = reports that something happened. }}