wiki:TBR/BSP/Rad750

Version 15 (modified by Jennifer, on Jan 21, 2011 at 12:27:10 AM) (diff)

Rad750

<!-- When filling in the box,

+ Try to include links to other Wiki pages and websites. + If a field is not applicable, not setting the variable will result in it not being displayed + If Simulator is not set, then No. is displayed.

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{{Infobox BSP |BSP_name = RAD750 |Manufacturer = BAE |image = Bae cimg eis rad750 family.jpg |caption = RAD750 3U, CPU, and 6U |Board_URL = http://www.baesystems.com/ProductsServices/bae_prod_s2_rad750.html |Architecture = PowerPC |CPU_model = RAD750 |Monitor = SUROM |Simulator = None freely available |Aliases = rad750_3u, rad750_6u, rad750_3u_debug, and rad750_6u_debug |RAM = 128 MB |NVMEM = XX KB EEPROM |Serial = one. NS16550 compatible |NICs = None |Video = None |Other = Radiation Hardened }}

Overview

The BAE Systems RAD750 Single Board Computer contains a RAD750 PowerPC cpu and a Power PCI intelligent bridge with peripherals. This bsp uses a large amount of shared functionality since this cpu is a hardened version of the the PowerPC 750, the Power PCI contains a ns16550 compatible UART, and the Power PCI appears to be PReP compliant. At this time there are four supported configurations across two boards to allow building for 3U or 6U in production and debug configurations. The debug configurations are built with options which make it possible to debug using the Corelis JTAG emulator. The following lists the BSP variants:

  • rad750_3u - 3U board, production build
  • rad750_6u - 6U board, production build
  • rad750_3u_debug - 3U board, debug build
  • rad750_6u_debug - 6U board, debug build

The configuration settings for the BSP variants are as follows:

{| border="1" style="margin: 1em auto 1em auto;text-align: center;" |+

|BSP Variant | rad750_3u | rad750_3u_debug | rad750_6u | rad750_6u_debug
rad750_3u rad750_6u BSP_DIRTY_MEMORY BSP_PRESS_KEY_FOR_RESET
defined undefined 0 1
defined undefined 0 0
undefined defined 0 1
undefined defined 0 0

|}

The constants are defined as follows:

  • BSP_DIRTY_MEMORY - When set to 1, the BSP Framework will not put a non-zero pattern into the RTEMS Workspace and C program heap.

=

  • BSP_PRESS_KEY_FOR_RESET = 0 The application will not print a message and wait until pressed before resetting board when application exits
  • BSP_RESET_BOARD_AT_EXIT = 1 The board will be reset when the application exits.
  • CONSOLE_USE_INTERRUPTS = 0 The console operates in polled mode
  • ENABLE_SHADOWED_DATA = 1 A sh ==- When filling in the box, + Try to include links to other Wiki pages and websites. + If a field is not applicable, not setting the variable will result in it not being displayed + If Simulator is not set, then No. is displayed.

-->

{{Infobox BSP |BSP_name = RAD750 |Manufacturer = BAE |image = Bae cimg eis rad750 family.jpg |caption = RAD750 3U, CPU, and 6U |Board_URL = http://www.baesystems.com/ProductsServices/bae_prod_s2_rad750.html |Architecture = PowerPC |CPU_model = RAD750 |Monitor = SUROM |Simulator = None freely available |Aliases = rad750_3u, rad750_6u, rad750_3u_debug, and rad750_6u_debug |RAM = 128 MB |NVMEM = XX KB EEPROM |Serial = one. NS16550 compatible |NICs = None |Video = None |Other = Radiation Hardened }}

Overview

The BAE Systems RAD750 Single Board Computer contains a RAD750 PowerPC cpu and a Power PCI intelligent bridge with peripherals. This bsp uses a large amount of shared functionality since this cpu is a hardened version of the the PowerPC 750, the Power PCI contains a ns16550 compatible UART, and the Power PCI appears to be PReP compliant. At this time there are four supported configurations across two boards to allow building for 3U or 6U in production and debug configurations. The debug configurations are built with options which make it possible to debug using the Corelis JTAG emulator. The following lists the BSP variants:

  • rad750_3u - 3U board, production build
  • rad750_6u - 6U board, production build
  • rad750_3u_debug - 3U board, debug build
  • rad750_6u_debug - 6U board, debug build

The configuration settings for the BSP variants are as follows:

{| border="1" style="margin: 1em auto 1em auto;text-align: center;" |+

|BSP Variant | rad750_3u | rad750_3u_debug | rad750_6u | rad750_6u_debug
rad750_3u rad750_6u BSP_DIRTY_MEMORY BSP_PRESS_KEY_FOR_RESET
defined undefined 0 1
defined undefined 0 0
undefined defined 0 1
undefined defined 0 0

|}

The constants are defined as follows:

  • BSP_DIRTY_MEMORY - When set to 1, the BSP Framework will not put a non-zero pattern into the RTEMS Workspace and C program heap.

=

  • BSP_PRESS_KEY_FOR_RESET = 0 The application will not print a message and wait until pressed before resetting board when application exits
  • BSP_RESET_BOARD_AT_EXIT = 1 The board will be reset when the application exits.
  • CONSOLE_USE_INTERRUPTS = 0 The console operates in polled mode
  • ENABLE_SHADOWED_DATA = 1 A shadow copy of initialized data is made on the first run and is reloaded on subsequent runs.
  • ENHANCED_PPCI = 1 Indicating that the board has the enhanced PPCI chip
  • PPC_USE_DATA_CACHE = 0 Data cache is disabled
  • PPC_USE_INSTRUCTION_CACHE = 1 Instruction cache is enabled
  • SHOW_PCI_SETTING = 0 Does not Print out PCI findings during initialization.

The production build for the 3u adds the following:

  • rad750_3u = 1 Selects 6u specific source

The production build for the 6u adds the following:

  • rad750_6u = 1 Selects 6u specific source

The debug build for the 3u and the 6u have the following settings:

  • BSP_DIRTY_MEMORY = 0 The BSP Framework will not put a non-zero pattern into the RTEMS Workspace and C program heap.
  • BSP_PRESS_KEY_FOR_RESET = 0 The application will not print a message and wait until pressed before resetting board when application exits
  • BSP_RESET_BOARD_AT_EXIT = 0 The board will not be reset when the application exits.
  • CONSOLE_USE_INTERRUPTS = 0 The console operates in polled mode
  • ENABLE_SHADOWED_DATA = 1 A shadow copy of initialized data is made on the first run and is reloaded on subsequent runs.
  • ENHANCED_PPCI = 1 Indicating that the board has the enhanced PPCI chip
  • PPC_USE_DATA_CACHE = 0 Data cache is disabled
  • PPC_USE_INSTRUCTION_CACHE = 0 Instruction cache is disabled
  • SHOW_PCI_SETTING = 1 Prints out PCI findings during initialization.

The debug build for the 3u adds the following:

  • rad750_3u = 1 Selects 6u specific source

The debug build for the 6u adds the following:

  • rad750_6u = 1 Selects 6u specific source

Board Setup

If there are special jumper or ROM monitor settings, describe them.

=Downloading and Executing=

Describe the download procedure.

=Debugging=

How do you debug code on this board? What gdb setup? BDM, stub, etc?

=Test Reports=

{{Test Report |Version = CVS head |Date = DATE |User = User:WhoTestedThis? |Report = reports that something happened. }}

=References=

{{Navbox_BSPs}}