Changes between Version 6 and Version 7 of TBR/BSP/QorIQ


Ignore:
Timestamp:
Nov 9, 2018, 3:57:45 AM (11 months ago)
Author:
shashvat jain
Comment:

Fixed Infobox

Legend:

Unmodified
Added
Removed
Modified
  • TBR/BSP/QorIQ

    v6 v7  
    33QorIQ is a brand of Power Architecture-based communications microprocessors from Freescale. They span the market with a broad  range of solutions from single to dual to multicore devices. These products are all built on Power Architecture® technology and include both 45 and 28 nm process technologies
    44
    5 {{Infobox BSP
    6 |BSP_name     = QorIQ
    7 |Manufacturer = Freescale
    8 |image        = P2010RDB.jpg
    9 |Board_URL    = http://www.freescale.com/webapp/sps/site/homepage.jsp?code=QORIQ_HOME (or)
    10                 http://www.freescale.com/files/32bit/doc/prod_brief/P4080PB.pdf
    11 |Architecture = Power Architecture
    12 |CPU_model    = QorIQ P4080 – 8-core CPU @ 1.5GHz
    13 |Simulator    = Only for P4080
    14 |Aliases      = P4080
    15 |RAM          = Two 64-bit DDR2/DDR3 SDRAM memory controllers up to 8 GB RAM with ECC and interleaving support
    16 |NVMEM        = Three level cache-hierarchy: 32 KB I/D L1, 128 KB private L2 per core, 2 MB shared L3
    17 |Serial       = Two Serial RapidIO® 1.2 controllers/ports running at up to 3.125 GHz
    18 |Video        = http://www.youtube.com/watch?v=sC8zaeL66GM (or)
    19                 http://www.youtube.com/watch?v=f0YUJ-fXxHA
    20 }}
     5== Infobox BSP ==
     6||'''BSP_name'''     ||QorIQ||
     7||'''Manufacturer''' ||Freescale||
     8||'''image'''        ||P2010RDB.jpg||
     9||'''Board_URL'''    ||http://www.freescale.com/webapp/sps/site/homepage.jsp?code=QORIQ_HOME (or)http://www.freescale.com/files/32bit/doc/prod_brief/P4080PB.pdf||
     10||'''Architecture''' ||Power Architecture||
     11||'''CPU_model'''    ||QorIQ P4080 – 8-core CPU @ 1.5GHz||
     12||'''Simulator'''    ||Only for P4080||
     13||'''Aliases'''      ||P4080||
     14||'''RAM'''          ||Two 64-bit DDR2/DDR3 SDRAM memory controllers up to 8 GB RAM with ECC and interleaving support||
     15||'''NVMEM '''       ||Three level cache-hierarchy: 32 KB I/D L1, 128 KB private L2 per core, 2 MB shared L3||
     16||'''Serial '''      ||Two Serial RapidIO® 1.2 controllers/ports running at up to 3.125 GHz||
     17||'''Video'''        ||http://www.youtube.com/watch?v=sC8zaeL66GM (or)http://www.youtube.com/watch?v=f0YUJ-fXxHA||
    2118
    2219= Overview =
     
    2522 *  [http://en.wikipedia.org/wiki/QorIQ QorIQ on Wikipedia]
    2623 *  [http://www.rtems.org/wiki/index.php/Qoriq QorIQ on RTEMS Wiki]
     24
    2725
    2826= Tested Variants =