| | 50 | |
| | 51 | = Series = |
| | 52 | |
| | 53 | Freescale introduced the first QorIQ P series products in 2008. Today, they have more than |
| | 54 | twenty P1–P5 products in the market. The next generation of processors, the Advanced Multiprocessing (AMP) series was recently |
| | 55 | announced with products beginning in 2012. These processors will be designated as T1–T5 |
| | 56 | |
| | 57 | = P Series = |
| | 58 | |
| | 59 | = P1 = |
| | 60 | |
| | 61 | The QorIQ P1 platform series, which includes the P1020 and P1011 communications processors, offers the value of extensive integration and extreme power for a wide variety of applications in the networking, telecom, aerospace, defense and industrial markets. The series provides dual-and single-core solutions for the 533 MHz to 800 MHz performance range, along with advanced security and a rich set of interfaces delivered on 45 nm technology for a low-power implementation. |
| | 62 | |
| | 63 | The P1 platform series is perfectly suited for multiservice gateways, Ethernet switch controllers, wireless LAN access points and high-performance general-purpose control processor applications with tight thermal constraints. |
| | 64 | |
| | 65 | The QorIQ P1 series consists of dual- and single-core products that are pin-compatible with QorIQ P2 platform products, offering a five-chip range of cost-effective solutions. Scaling from a single core at 533 MHz (P1011) to a dual core at 1.2 GHz per core (P2020), the two QorIQ platforms deliver an impressive 4.5X aggregate frequency range. |
| | 66 | |
| | 67 | '''Features:''' |
| | 68 | * Dual (P1020) or single (P1011) high-performance Power Architecture® e500 cores, 32 KB L1 cache, up to 800 MHz |
| | 69 | * 32-bit DDR2/DDR3 SDRAM memory controller with ECC support |
| | 70 | * 256 KB L2 cache with ECC. Also configurable as SRAM and stashing memory |
| | 71 | * Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs) |
| | 72 | * High-speed interfaces supporting various multiplexing options: |
| | 73 | * Four SerDes up to 3.125 GHz multiplexed across controllers |
| | 74 | * Two PCI Express® interfaces |
| | 75 | * Two SGMII interfaces |
| | 76 | * Dual high-speed USB controllers (USB 2.0) |
| | 77 | |
| | 78 | = P2 = |
| | 79 | |
| | 80 | The QorIQ P2 platform series, which includes the P2020 and P2010 communications processors, delivers high single-threaded performance per watt for a wide variety of applications in the networking, telecom, military and industrial markets. The series delivers dual- and single-core frequencies up to 1.2 GHz on a 45 nm technology low-power platform. |
| | 81 | |
| | 82 | The QorIQ P2 series consists of dual- and single-core products that are pin-compatible with the QorIQ P1 platform products, offering a five interchangeable cost-effective solutions. Scaling from a single core at 533 MHz (P1011) to a dual core at 1.2 GHz (P2020), the two QorIQ platforms together deliver an impressive 4.5x aggregate frequency range within the same pinout. |
| | 83 | |
| | 84 | The P2020 and P2010 communications processors both have an advanced set of features for ease of use. The integrated security engine supports common security algorithms used in networking and wireless applications, such as IPsec and Kasumi. The 64-bit memory controller offers future-proofing against memory technology migration with support for both DDR2 and DDR3. It also supports error correction codes, a baseline requirement for any high-reliability system. Other memory types such as flash are supported through the 16-bit local bus, USB, SD/MMC and serial peripheral interface (SPI). |
| | 85 | |
| | 86 | '''Features:''' |
| | 87 | * Dual (P2020) or single (P2010) high-performance Power Architecture® e500 cores, 32 KB L1 cache, up to 1.2 GHz |
| | 88 | * 32/64-bit DDR2/DDR3 SDRAM memory controller with ECC support |
| | 89 | * 512 KB L2 cache with ECC. Also configurable as SRAM and stashing memory |
| | 90 | * Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs) |
| | 91 | * High-speed interfaces supporting various multiplexing options: |
| | 92 | * Four SerDes up to 3.125 GHz multiplexed across controllers |
| | 93 | * Two PCI Express® interfaces |
| | 94 | * Two Serial RapidIO® interfaces |
| | 95 | * Two SGMII interfaces |
| | 96 | * Dual high-speed USB controllers (USB 2.0) |
| | 97 | |
| | 98 | = P3 = |
| | 99 | |
| | 100 | The QorIQ P3041 processor is an optimized quad-core device that leverages architectural features pioneered in the P4 platform. Built on Power Architecture® technology the P3041 fits into many of the same applications as the P4 platform processors, yet is designed to offer a more power- and cost-efficient solution. |
| | 101 | |
| | 102 | The P3041 includes P4 platform features such as the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet switch fabric which eliminates internal bottlenecks. This enables architectural compatibility from the P3041 to the P4 platform and also to the P5 platform, which uses the same architecture. P3041 is pin compatible with P4040, P4080, P5010, and P5020. |
| | 103 | |
| | 104 | '''Features:''' |
| | 105 | * Four high-performance e500mc cores up to 1.5 GHz |
| | 106 | * Three level cache-hierarchy: 32 KB I/D L1, 128 KB private L2 per core, 1 MB shared CorNet platform cache |
| | 107 | * 64-bit (72-bit with ECC) DDR2/3 memory controller up to 1.3 GHz datarate |
| | 108 | * DPAA incorporating acceleration for the following functions: |
| | 109 | * Packet parsing, classification, and distribution |
| | 110 | * Queue management for scheduling, packet sequencing, and congestion management |
| | 111 | * Hardware buffer management for buffer allocation and de-allocation |
| | 112 | * Encryption (SEC 4.2) |
| | 113 | * RegEx Pattern Matching (PME 2.1) |
| | 114 | * Ethernet interfaces: |
| | 115 | * One 10 Gbps Ethernet (XAUI) controllers |
| | 116 | * Five 1 Gbps Ethernet controllers available on SGMII, 2.5Gbps SGMII, or RGMII |
| | 117 | * High-speed peripheral interfaces: |
| | 118 | * Four PCI Express® v2.0 controllers/ports running at up to 5 GHz |
| | 119 | * Two Serial RapidIO® 1.3/2.1 controllers/ports running at up to 5 GHz, with Type 9 and 11 messaging |
| | 120 | * Two SATA 2.0 interfaces |
| | 121 | |
| | 122 | = P4 = |
| | 123 | |
| | 124 | The QorIQ P4080 processor, the first product offered in the QorIQ P4 platform series, delivers industry-leading performance in the under 30-watt power category. It combines eight Power Architecture® e500mc cores—operating at frequencies up to 1.5 GHz—with high-performance datapath acceleration logic and network and peripheral bus interfaces designed for 45 nm technology to deliver high-performance, next-generation networking services in a very low-power envelope. |
| | 125 | |
| | 126 | The QorIQ P4080 processor can be used for combined control, datapath and application layer processing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while greatly simplifying board design. The processor is well-suited for applications that are highly compute-intensive, I/O intensive or both, making it ideal for applications such as enterprise and service provider routers, switches, base station controllers, radio network controllers (RNCs), long term evolution (LTE) and general-purpose embedded computing systems in the networking, telecom/datacom, wireless infrastructure, military and aerospace markets. |
| | 127 | |
| | 128 | '''Features:''' |
| | 129 | * Eight high-performance e500mc cores up to 1.5 GHz |
| | 130 | * Three level cache-hierarchy: 32 KB I/D L1, 128 KB private L2 per core, 2 MB shared L3 |
| | 131 | * Dual 64-bit (72-bit with ECC) DDR2/3 memory controllers up to 1.3 GHz data rate |
| | 132 | * DPAA incorporating acceleration for the following functions: |
| | 133 | * Packet parsing, classification, and distribution |
| | 134 | * Queue management for scheduling, packet sequencing, and congestion management |
| | 135 | * Hardware buffer management for buffer allocation and de-allocation |
| | 136 | * Encryption (SEC 4.0) |
| | 137 | * RegEx Pattern Matching (PME 2.0) |
| | 138 | * Ethernet interfaces: |
| | 139 | * Two 10 GBps Ethernet (XAUI) controllers |
| | 140 | * Eight 1 GBps Ethernet (SGMII) controllers |
| | 141 | * High-speed peripheral interfaces: |
| | 142 | * Three PCI Express® v2.0 controllers/ports running at up to 5 GHz |
| | 143 | * Two Serial RapidIO® 1.2 controllers/ports running at up to 3.125 GHz |
| | 144 | |
| | 145 | The QorIQ P4040 processor, the second product offered in the QorIQ P4 platform series, delivers industry-leading performance in a real-world embedded power envelope. It combines four Power Architecture® e500mc cores—operating at frequencies up to 1.5 GHz—with high-performance data path acceleration architecture (DPAA), CoreNet fabric infrastructure and network and peripheral bus interfaces. Designed in 45 nm technology, the P4040 delivers high-performance, next-generation networking services in a very low-power envelope—some 30 to 35 percent less than the original QorIQ P4080 processor. |
| | 146 | |
| | 147 | The QorIQ P4040 processor is designed to be used for combined control, data path, and application layer processing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while also greatly simplifying board design. The processor is well-suited for applications that are highly compute-intensive, I/O intensive or both. |
| | 148 | |
| | 149 | '''Features:''' |
| | 150 | * Four high-performance e500mc cores up to 1.5 GHz |
| | 151 | * Three level cache-hierarchy: 32 KB I/D L1; 128 KB private L2 per core; 2 MB shared L3 |
| | 152 | * Dual 64-bit (72-bit with ECC) DDR2/3 memory controllers up to 1.3 GHz data rate |
| | 153 | * DPAA incorporating acceleration for the following functions: |
| | 154 | * Packet parsing, classification and distribution |
| | 155 | * Queue management for scheduling, packet sequencing, and congestion management |
| | 156 | * Hardware buffer management for buffer allocation and de-allocation |
| | 157 | * Encryption (SEC 4.0) |
| | 158 | * RegEx Pattern Matching (PME 2.0) |
| | 159 | * Ethernet interfaces: |
| | 160 | * Two 10 GBps Ethernet (XAUI) controllers |
| | 161 | * Eight 1 GBps Ethernet (SGMII) controllers |
| | 162 | * High-speed peripheral interfaces: |
| | 163 | * Three PCI Express® v2.0 controllers/ports running at up to 5GHz |
| | 164 | * Two Serial RapidIO® 1.2 controllers/ports running at up to 3.125 GHz |
| | 165 | = P5 = |
| | 166 | |
| | 167 | The dual-core P5020 and single-core P5010 processors are Freescale’s first offerings with the 64-bit, e5500 core built on Power Architecture® technology. With frequencies scalable to 2.2 GHz, large caches and high per-cycle efficiency, these products target control plane and compute applications that require high single-threaded performance. |
| | 168 | |
| | 169 | The P5 platform leverages architectural features pioneered in the P4 platform, including the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet switch fabric that eliminates internal bottlenecks. This enables architectural compatibility from the P5 platform to the P4 platform as well as to the P3 platform. |
| | 170 | |
| | 171 | '''Features:''' |
| | 172 | * Single or dual 64-bit e5500 cores initially offered at 2.0GHz and scalable to 2.2 GHz |
| | 173 | * Three level cache-hierarchy: 32 KB I/D L1; 512 KB private L2 per core; 2 MB shared L3 |
| | 174 | * Dual 64-bit (72-bit with ECC) DDR3/3L memory controllers to 1.3 GHz data rate |
| | 175 | * 18 SerDes lanes up to 5 GHz, supporting 4x PCI Express® 2.0, 2x Serial RapidIO® (1.3+2.1), XAUI, 5x SGMII/2.5Gbps SGMII, 2x serial ATA 2.0, Aurora debug port |
| | 176 | * Hardware acceleration: |
| | 177 | * Frame manager for packet handling |
| | 178 | * Queue manager for policing, scheduling and workload distribution |
| | 179 | * Pattern matching engine for regular expression seaches |
| | 180 | * RAID5/6 for parity calculations in storage applications |
| | 181 | * Security block for crypto algorithm acceleration |
| | 182 | * RapidIO message manager for type 9 and 11 messaging |
| | 183 | = Qonverge = |
| | 184 | |
| | 185 | The QorIQ Qonverge PSC9130 and PSC9131 processors are highly integrated devices that target the evolving femto and enterprise-femto applications. Both the PSC9130 and PSC9131 devices combines Power e500 and StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing, addressing the need for a high-performance, low-cost, integrated solution, that handles all the digital-baseband processing required for femtocells. |
| | 186 | |
| | 187 | The programmable PSC9130 and PSC9131 devices, targeted at LTE-FDD/TDD and WCDMA (HSPA+), supports multiple air interface standards and can support two concurrent standards. |
| | 188 | |
| | 189 | '''Features:''' |
| | 190 | * Power Architecture subsystem including one e500 processor and 256-Kbyte shared L2 cache |
| | 191 | * StarCore SC3850 DSP subsystem including 512-Kbyte private L2 cache |
| | 192 | * The MAPLE-B2F multi-accelerator platform engine supports functions that enable LTE-FDD/TDD, WiMAX, WCDMA/HSPA+ and CDMA2K wireless standards |
| | 193 | * DDR3 memory interface with 32-bit data width (40 bits including ECC), up to 800-MHz data rate |
| | 194 | * Integrated Flash controller for NOR, NAND, and FPGA support |
| | 195 | * Dedicated security engine featuring trusted boot |
| | 196 | * Two RF interfaces supporting JESD207 (ADI) |
| | 197 | * Two pulse width modulators (PWM) for control of external components |
| | 198 | * Support of MaxPhy interface (Maxim) |
| | 199 | * Two triple-speed Gigabit-Ethernet controllers featuring network acceleration including IEEE Std 1588v2™ hardware support |
| | 200 | * USB 2.0 host and device controller |
| | 201 | * DMA controller with four bidirectional channels that serves both the Power Architecture cores and DSP domains |
| | 202 | * UART, SPI, eSDHC, USIM, and I2C controllers |
| | 203 | * GPIO, Sixteen 32-bit timers |
| | 204 | |
| | 205 | = AMP = |
| | 206 | |
| | 207 | The QorIQ Advanced Multiprocessing, AMP Series, processors are all based on the multithreaded 64-bit e6500 core with integrated AltiVec SIMD processing units. Products will range from single core versions up to parts with 12 cores or more with frequencies ranging all the way up to 2.5 GHz. The processes will be sectioned into five classes according to performance and features, named T1 through T5, and will be manufactured in a 28 nm process beginning in 2012.= =T4 == |
| | 208 | |
| | 209 | T4240 – The first product announced and will incorporate twelve e6500 dual-threaded cores, four memory controllers and various other accelerators. |
| | 210 | |
| | 211 | = References = |
| | 212 | |
| | 213 | http://en.wikipedia.org/wiki/QorIQ |
| | 214 | |
| | 215 | http://www.freescale.com/webapp/sps/site/homepage.jsp?code=QORIQ_HOME |
![[RTEMS Logo]](/images/logo.png){kind=logo}
