wiki:TBR/BSP/Psim

Version 36 (modified by E.begov, on 12/02/10 at 20:28:11) (diff)

Psim

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{{Infobox BSP |BSP_name = Motorola (now Emerson) |Manufacturer = Motorola |image = Motorola_MVME5500_151626_View1.jpg? |caption = optional image caption |Board_URL = http:/manufacturer.com/ExampleBoard |Architecture = Architecture |CPU_model = 1 GHz MPC7455 processor |Monitor = uBoot, uMon |Simulator = Yes. Skyeye |RAM = 512 MB |NVMEM = 2MB using DDR SRAM |Serial = one. UART part name. |NICs = one. NIC part name. |Other = anything else you need to say }}

Overview

The MVME5500 is a single-board computer based on the PowerPC MPC7455 processor and the Marvell GT-64260B host bridge with a dual PCI interface and memory controller. On-board payload includes two PMC slots, two SDRAM banks, an expansion connector for two additional banks of SDRAM, 8MB boot Flash ROM, one 10/100/1000 Ethernet port, one 10/100 Ethernet port, 32MB expansion Flash ROM, two serial ports, NVRAM and a real-time clock. The MVME5500 interfaces to a VMEbus system via its P1 and P2 connectors and contains two IEEE 1386.1 PCI mezzanine card (PMC) slots. The PMC slots are 64-bit and support both front and rear I/O. Additionally, the MVME5500 is user-configurable by setting on-board jumpers. Two I/O modes are possible: PMC mode or SBC mode (also called 761 or IPMC mode). The SBC mode uses the IPMC712 I/O PMC and the MVME712M transition module, or the IPMC761 I/O PMC and the MVME761 transition module. The SBC mode is backwards compatible with the MVME761 transition module and the P2 adapter card (excluding PMC I/O routing) used on the MVME5100 product. This mode is accomplished by configuring the on-board jumpers and by attaching an IPMC761 PMC in PMC slot 1. Secondary Ethernet is configured to the rear. PMC mode is backwards compatible with the MVME5100 and is accomplished by configuring the on-board jumpers.

SPECIFICATIONS

Processor

  • Microprocessor: MPC7455
  • Clock Frequency: 1 GHz
  • On-chip L1 Cache (I/D): 32KB/32KB
  • On-chip L2 Cache (I/D): 256KB/256KB
  • L3 Cache: 2MB

Flash Memory

  • Type: EEPROM, on-board programmable
  • Capacity: 8MB via two 56-pin TSOP sockets; 32MB

soldered Flash

  • Write Protection: 32MB of surface-mount Flash is write-

protectable via jumper

System Controller

  • Marvell Discovery GT-64260A

Board Setup

If there are special jumper or ROM monitor settings, describe them.

Debugging

The MVME5500 provides a boundary scan header (J18) and a COP (Riscwatch) header for debug capability.

Test Reports

Motorola Built-In Test (MBIT) software is available for use on the MVME5500 series. MBIT is an off-the-shelf software infrastructure designed to verify correct operation of Motorola hardware and enable the incorporation of system-level diagnostics. Two versions of MBIT, board-level and system-level, are available and are compatible with WindRiver? Systems Tornado 2.1. The board-level MBIT is a comprehensive diagnostic software package designed to verify the performance of board- mounted logic devices. All tests can execute at boot-up, while selected tests can run continuously in the background of user applications. An application programming interface (API) is included to provide access to test results and to modify and control the operation of device tests. A comprehensive user’s manual is available. The system-level MBIT includes all functionality and API function calls of the board-level version and enables system-wide testing. The system-level MBIT provides a framework and additional API function calls to support the inclusion of software designed to test custom hardware and/or system components. A comprehensive user’s manual with software development guidelines is available.

References

  • TBD

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