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Changes between Version 18 and Version 19 of TBR/BSP/Psim


Ignore:
Timestamp:
12/02/10 18:55:25 (14 years ago)
Author:
E.begov
Comment:

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  • TBR/BSP/Psim

    v18 v19  
    1616|Board_URL    = http:/manufacturer.com/ExampleBoard
    1717|Architecture = Architecture
    18 |CPU_model    = MPC7455
     18|CPU_model    = 1 GHz MPC7455 processor
    1919|Monitor      = uBoot, uMon
    2020|Simulator    = Yes. [wiki:Developer/Simulators/SkyEye  Skyeye]
    21 
    2221|RAM          = 512 MB
    2322|NVMEM        = 256KB of on-chip L2 cache and 2MB of L3 cache