wiki:TBR/BSP/Ppc405ex

Version 6 (modified by Mhamel, on Jan 12, 2009 at 7:28:06 AM) (diff)

/* Downloading and Executing */

Ppc405ex

{{Infobox BSP |image = |BSP_name = haleakala |Manufacturer = AMCC/UDTech |Architecture = PowerPC |CPU_model = PPC405EX/EXr |Aliases = kileaua |RAM = 256M |NICs = 1/2 |Serial_ports = 2 }}

Overview

This BSP supports boards based on the AMCC PPC405EX and 405EXr processors. It is derived from the 405-generic code but uses the new interrupt handling.

This BSP is known to work (4.9.1) on the Haleakala board (PPC405EXr, one Ethernet port) and should function on the Kileaua board (same board, PPC405EX and two Ethernet ports).

The BSP has a few lines of code writing to an onboard FPGA which are specific to the Haleakala/Kileaua? boards, but is otherwise suitable as a generic 405EX/EXR platform.

Work on a network interface for the PPC405EX/EXr/GP/GPr is underway (it functions, but needs testing)

Board Setup

If there are special jumper or ROM monitor settings, describe them.

Downloading and Executing

This BDM is designed to be downloaded directly into DRAM via a Macraigor OCDemon BDM device. This means that the DRAM controller has to be set up first so that we have some working RAM to write to. The following gdb script does this; other loading methods need to prefix equivalent code to dlentry.S

# Common gdb setup for PowerPC CPUs
set complaints 1
set output-radix 10
set input-radix 10
set prompt (powerpc-gdb) 
set architecture rs6000:rs2
set endian big
dir .

define sdram_set
	monitor dcr 0x10=$arg0
	monitor dcr 0x11=$arg1
end


define sdram_init
# Derived from Haleakala EVB users manual 3.3.1 plus check against EVB values
	sdram_set	0x40	0x6701		
# MB0CF base addr 0, 256M Nx10, 8 bank
	sdram_set	0x44	0			
# MB1CF not enabled
	sdram_set	0x80	0x80000000	
# CLKTR advance clock 180 degrees
	sdram_set	0x30	0x06180000	
# RTR:  1560 tCk = 7.8 usec
	sdram_set	0x85	0x80201000	
# SDTR1
	sdram_set	0x86	0x32204232	
# SDTR2
	sdram_set	0x87	0x080B0D1A	
# SDTR3
	sdram_set	0x88	0x00000442	
# MMODE
	sdram_set	0x89	0x00000404	
# MEMODE
	sdram_set	0x20	0x04322000	
# MCOPT1: No ECC
	sdram_set	0x50	0xA8380000	
# InitPLR0 No-op, wait min 400nsec
	sdram_set	0x51	0x81900400	
# INITPLR1 Precharge all wait min 3 cycle
	sdram_set	0x52	0x81020000	
# INITPLR2
	sdram_set	0x53	0x81030000
	sdram_set	0x54	0x81010404
	sdram_set	0x55	0x81000542
	sdram_set	0x56	0x81900400
	sdram_set	0x57	0x8d080000	
# INITPLR7
	sdram_set	0x58	0x8d080000
	sdram_set	0x59	0x8d080000
	sdram_set	0x5A	0x8d080000
	sdram_set	0x5B	0x81000442
	sdram_set	0x5C	0x81010780
	sdram_set	0x5D	0x81010400	
# INITPLR13
	sdram_set	0x5E	0			
# INITPLR14
	sdram_set	0x5F	0			
# INITPLR15
	sdram_set	0x26	0x0080F837	
# CODT
	sdram_set	0x22	0x01800000	
# MODT0
	sdram_set	0x81	0			
# WRDTR
	sdram_set	0x21	0x20000000	
# MCOPT2: Start initialisation. Delay 100 usec here
	sdram_set	0x7A	0x03000086	
# DLCR	// was ...A5
	sdram_set	0x78	0x40000000	
# RDCC
	sdram_set	0x70	0x80000038	
# RQDC
	sdram_set	0x74	0x00000209	
# RFDC
	sdram_set	0x21	0x08000000	
# MCOPT2, enable controller
end

# CONNECT TO TARGET : this is the IP address of the PC running Macraigor software
# with USB2Sprite connected to running target
# Command to Cygwin on the PC is:
# $ /usr/local/bin/ocdremote -c PPC405 -d USB

target remote tcp:10.0.1.2:8888

# Reset Target board
monitor reset
flushregs

# Initialise SDRAM controller so we have RAM to work with
sdram_init

# Load the file and run to start point
load o-optimize/netdemo.exe
symbol-file o-optimize/netdemo.exe

Debugging

How do you debug code on this board? What gdb setup? BDM, stub, etc?

Test Reports

{{Test Report |Version = TBD |Date = TBD |User = TBD |Report = TBD }}

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