wiki:TBR/BSP/Ppc405ex

Version 5 (modified by JoelSherrill, on Jan 9, 2009 at 5:28:42 AM) (diff)

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Ppc405ex

{{Infobox BSP |image = |BSP_name = haleakala |Manufacturer = AMCC/UDTech |Architecture = PowerPC |CPU_model = PPC405EX/EXr |Aliases = kileaua |RAM = 256M |NICs = 1/2 |Serial_ports = 2 }}

Overview

This BSP supports boards based on the AMCC PPC405EX and 405EXr processors. It is derived from the 405-generic code but uses the new interrupt handling.

This BSP is known to work (4.9.1) on the Haleakala board (PPC405EXr, one Ethernet port) and should function on the Kileaua board (same board, PPC405EX and two Ethernet ports).

The BSP has a few lines of code writing to an onboard FPGA which are specific to the Haleakala/Kileaua? boards, but is otherwise suitable as a generic 405EX/EXR platform.

Work on a network interface for the PPC405EX/EXr/GP/GPr is underway (it functions, but needs testing)

Board Setup

If there are special jumper or ROM monitor settings, describe them.

Downloading and Executing

Describe the download procedure.

Debugging

How do you debug code on this board? What gdb setup? BDM, stub, etc?

Test Reports

{{Test Report |Version = TBD |Date = TBD |User = TBD |Report = TBD }}

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