Version 17 (modified by shashvat jain, on Nov 8, 2018 at 9:47:28 PM) (diff)

Fixed Infobox


Infobox BSP

BSP_name OR1200
Manufacturer OpenCores?
image Or1200_blocks.png
Architecture OpenRISC
CPU_model 32-bit Scalar (Harvard microarchitecture)20MHz on Actel ProASIC3, SDR SDRAM
Monitor uBoot, uMon
Simulator Yes. Skyeye, FPGA or ASIC
Aliases OR1200
RAM 8KByte/4KByte I/D cache and a default size of 64 entries
Serial UART 16550
Video 2 channel video DAC PS2 interface

This BSP supports a simulator for the OpenCores? CPU.

This BSP was removed along with the OR32 port after the RTEMS 4.6 release series.

The port is revived in 2014.