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Version 16 (modified by Hesham Almatary, on 03/14/15 at 10:42:56) (diff)



{{Infobox BSP |BSP_name = OR1200 |Manufacturer = OpenCores? |image = Or1200_blocks.png |Board_URL = |Architecture = OpenRISC |CPU_model = 32-bit Scalar (Harvard microarchitecture)20MHz on Actel ProASIC3, SDR SDRAM |Monitor = uBoot, uMon |Simulator = Yes. Skyeye, FPGA or ASIC |Aliases = OR1200 |RAM = 8KByte/4KByte I/D cache and a default size of 64 entries |NVMEM = |Serial = UART 16550 |Video = 2 channel video DAC PS2 interface }} This BSP supports a simulator for the OpenCores? CPU.

This BSP was removed along with the OR32 port after the RTEMS 4.6 release series.

The port is revived in 2014.