= Orp =


{{Infobox BSP
|BSP_name     = OR1200
|Manufacturer = OpenCores
|image        = ADSP BF537 STAMP color dark.jpg
|Board_URL    = http://opencores.org/or1k/OR1200_OpenRISC_Processor
|Architecture = OpenRISC
|CPU_model    = 32-bit Scalar (Harvard microarchitecture)
|Monitor      = uBoot, uMon
|Simulator    = Yes. [wiki:Developer/Simulators/SkyEye  Skyeye], FPGA or ASIC
|Aliases      = none
|RAM          = Not Found
|NVMEM        = 32 MB Flash, 16 KB EEPROM
|Serial       = one. UART part name.
|NICs         = one. NIC part name.
}}
This BSP supports a simulator for the [wiki:OpenCores OpenCores] CPU.

This BSP was removed along with the OR32 port after the RTEMS 4.6 release series.