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Changes between Version 4 and Version 5 of TBR/BSP/Orp


Ignore:
Timestamp:
01/12/13 07:36:21 (11 years ago)
Author:
.ayush10297
Comment:

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  • TBR/BSP/Orp

    v4 v5  
    88|Board_URL    = http://opencores.org/or1k/OR1200_OpenRISC_Processor
    99|Architecture = OpenRISC
    10 |CPU_model    = 32-bit Scalar (Harvard microarchitecture)
     10|CPU_model    = 32-bit Scalar (Harvard microarchitecture)20MHz on Actel ProASIC3, SDR SDRAM
    1111|Monitor      = uBoot, uMon
    1212|Simulator    = Yes. [wiki:Developer/Simulators/SkyEye  Skyeye], FPGA or ASIC
    13 |Aliases      = none
    14 |RAM          = Not Found
     13|Aliases      = OR1200
     14|RAM          = 8KByte/4KByte I/D cache and a default size of 64 entries
    1515|NVMEM        = 32 MB Flash, 16 KB EEPROM
    1616|Serial       = one. UART part name.
    17 |NICs         = one. NIC part name.
     17|Video        = http://www.youtube.com/watch?v=pbZNxo6o4lY
    1818}}
    1919This BSP supports a simulator for the [wiki:OpenCores OpenCores] CPU.