Changes between Version 1 and Version 2 of TBR/BSP/Orp


Ignore:
Timestamp:
01/09/13 05:40:02 (11 years ago)
Author:
Justinpotts
Comment:

This is work for a GCI 2012 task. I filled in the infobox.

Legend:

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  • TBR/BSP/Orp

    v1 v2  
    33
    44{{Infobox BSP
    5 |BSP_name     = Example BSP
    6 |Manufacturer = Who made me?
     5|BSP_name     = OR1200
     6|Manufacturer = OpenCores
    77|image        = ADSP BF537 STAMP color dark.jpg
    8 |caption      = optional image caption
    9 |Board_URL    = http:/manufacturer.com/ExampleBoard
    10 |Architecture = Architecture
    11 |CPU_model    = Model name
     8|Board_URL    = http://opencores.org/or1k/OR1K:Community_Portal
     9|Architecture = OpenRISC
     10|CPU_model    = 32-bit Scalar (Harvard microarchitecture)
    1211|Monitor      = uBoot, uMon
    1312|Simulator    = Yes. [wiki:Developer/Simulators/SkyEye  Skyeye]
    14 |Aliases      = Any RTEMS BSP Aliases?
    15 |RAM          = XXX MB
     13|Aliases      = none
     14|RAM          = Not Found
    1615|NVMEM        = 32 MB Flash, 16 KB EEPROM
    1716|Serial       = one. UART part name.
    1817|NICs         = one. NIC part name.
    19 |Other        = anything else you need to say
    2018}}
    2119This BSP supports a simulator for the [wiki:OpenCores OpenCores] CPU.