Changes between Version 16 and Version 17 of TBR/BSP/Orp


Ignore:
Timestamp:
Nov 8, 2018, 9:47:28 PM (11 months ago)
Author:
shashvat jain
Comment:

Fixed Infobox

Legend:

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  • TBR/BSP/Orp

    v16 v17  
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    4 {{Infobox BSP
    5 |BSP_name     = OR1200
    6 |Manufacturer = OpenCores
    7 |image        = Or1200_blocks.png
    8 |Board_URL    = http://opencores.org/or1k/OR1200_OpenRISC_Processor
    9 |Architecture = OpenRISC
    10 |CPU_model    = 32-bit Scalar (Harvard microarchitecture)20MHz on Actel ProASIC3, SDR SDRAM
    11 |Monitor      = uBoot, uMon
    12 |Simulator    = Yes. [wiki:Developer/Simulators/SkyEye  Skyeye], FPGA or ASIC
    13 |Aliases      = OR1200
    14 |RAM          = 8KByte/4KByte I/D cache and a default size of 64 entries
    15 |NVMEM        =
    16 |Serial       = UART 16550
    17 |Video        = 2 channel video DAC PS2 interface
    18 }}
     4== Infobox BSP ==
     5||'''BSP_name'''     ||OR1200||
     6||'''Manufacturer''' ||OpenCores||
     7||'''image'''        ||Or1200_blocks.png||
     8||'''Board_URL'''    ||http://opencores.org/or1k/OR1200_OpenRISC_Processor||
     9||'''Architecture''' ||OpenRISC||
     10||'''CPU_model'''    ||32-bit Scalar (Harvard microarchitecture)20MHz on Actel ProASIC3, SDR SDRAM||
     11||'''Monitor'''      ||uBoot, uMon||
     12||'''Simulator'''    ||Yes. [wiki:Developer/Simulators/SkyEye  Skyeye], FPGA or ASIC||
     13||'''Aliases'''      ||OR1200||
     14||'''RAM'''          ||8KByte/4KByte I/D cache and a default size of 64 entries||
     15||'''NVMEM'''        ||||
     16||'''Serial'''       ||UART 16550||
     17||'''Video'''        ||2 channel video DAC PS2 interface||
     18
    1919This BSP supports a simulator for the [wiki:OpenCores OpenCores] CPU.
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