wiki:TBR/BSP/Nios2_iss

Version 9 (modified by Ivaylo, on Dec 18, 2011 at 7:00:00 PM) (diff)

/* Processor */

Nios2 iss

Overview

Nios2 iss

Processor

Processor type: Fast (Nios /f)

  • 32-bit RISC
  • Instruction cache
  • Data cache
  • Branch prediction
  • Hardware multiply
  • Hardware divide
  • Barrel shifter
  • Dynamic branch prediction

Nominal metrics:

  • Nominal performance at 100 MHz: Up to 113 DMIPS
  • Nominal logic usage: 1400-1800 LEs
  • Nominal memory usage: Three M9K + Cache

Block diagram

{|align="center" |+Block diagram

|center? |}

References

http://www.altera.com/literature/hb/nios2/n2sw_nii52002.pdf

http://www.altera.com/products/devkits/altera/kit-cyc3-embedded.html

Attachments (2)

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