Nios2 iss

Overview

Nios2 iss

The microprocessor design is based on the Nios II/f core and provides a typical mix of peripherals, memories, and a video pipeline. The design provides an interface to each hardware component on the Altera Nios II Embedded Evaluation Kit, Cyclone III Edition, such as DDR SDRAM, LEDs, RS-232 connector, Ethernet MAC/10/100 PHY, and 800 × 480 pixel LCD. The video pipeline provides high bandwidth memory access that allows for flicker-free display on the color LCD.

Processor

The Nios II processor runs at a frequency of 100 MHz and is connected to high performance DDR SDRAM memory, on-chip descriptor memory, and CFI flash memory. Clock crossing bridges are required between the Nios II processor and the DDR SDRAM memory and slow peripherals components because these components run in different clock regions. A pipeline bridge between the Nios II processor and the flash tri-state bridge to external flash component ensures system fMAX is not affected and that every master sees every slave at the same address. The DDR SDRAM memory runs at 133 MHz. The ddr_sdram memory controller runs at half rate at local interface with a 64-bit data width, connected to a 32-bit width Nios II data bus and a 64-bit width SG-DMA through clock crossing bridges.

Processor type: Fast (Nios /f)

• 32-bit RISC
• Instruction cache
• Data cache
• Branch prediction
• Hardware multiply
• Hardware divide
• Barrel shifter
• Dynamic branch prediction

Nominal metrics:

• Nominal performance at 100 MHz: Up to 113 DMIPS
• Nominal logic usage: 1400-1800 LEs
• Nominal memory usage: Three M9K + Cache

Reset vector:

• Memory: ext_flash
• Offset: 0x0
• Physical address: 0x04000000

Exception vector:

• Memory: ssram
• Offset: 0x20
• Physical address: 0x05000020

I/O

Memory

Block diagram

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References

​http://www.altera.com/literature/hb/nios2/n2sw_nii52002.pdf

​http://www.altera.com/products/devkits/altera/kit-cyc3-embedded.html

​http://www.altera.com/literature/ds/ds_nios2_3c25_lcd.pdf