Nios2 iss

Overview

Nios2 iss

The microprocessor design is based on the Nios II/f core and provides a typical mix of peripherals, memories, and a video pipeline. The design provides an interface to each hardware component on the Altera Nios II Embedded Evaluation Kit, Cyclone III Edition, such as DDR SDRAM, LEDs, RS-232 connector, Ethernet MAC/10/100 PHY, and 800 × 480 pixel LCD. The video pipeline provides high bandwidth memory access that allows for flicker-free display on the color LCD.

Processor

Processor type: Fast (Nios /f)

• 32-bit RISC
• Instruction cache
• Data cache
• Branch prediction
• Hardware multiply
• Hardware divide
• Barrel shifter
• Dynamic branch prediction

Nominal metrics:

• Nominal performance at 100 MHz: Up to 113 DMIPS
• Nominal logic usage: 1400-1800 LEs
• Nominal memory usage: Three M9K + Cache

Block diagram

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References

​http://www.altera.com/literature/hb/nios2/n2sw_nii52002.pdf

​http://www.altera.com/products/devkits/altera/kit-cyc3-embedded.html