Changes between Version 37 and Version 38 of TBR/BSP/Nios2_iss


Ignore:
Timestamp:
Nov 13, 2018, 8:30:52 PM (7 months ago)
Author:
Sal
Comment:

fix format

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  • TBR/BSP/Nios2_iss

    v37 v38  
    5050
    5151The Altera programmed input/output (PIO) cores transfer data between the processor and certain input/output (I/O) devices. The microprocessor includes LED and Button PIOs. Table 7 shows the LED PIO parameters and corresponding parameter values.
    52 {|align="center"
    53 |-
    54 |[wiki:File:Io1.png center]
    55 |}
     52
     53[[Image(https://devel.rtems.org/old_images/Io1.png)]]
    5654
    5755Table 8 shows the Button PIO parameters and corresponding parameter values.
    58 {|align="center"
    59 |-
    60 |[wiki:File:Io2.png center]
    61 |}
     56[[Image(https://devel.rtems.org/old_images/Io2.png)]]
    6257= Memory =
    6358
     
    6661
    6762The Altera CFI-compliant flash memory controller core controls an external flash device (Intel). This flash device stores both application program code and FPGA configuration data. With 16 MByte capacity, it is possible to store multiple configuration images in flash memory and configure the FPGA with one of the images.
    68 {|align="center"
    69 |-
    70 |[wiki:File:Cfi.png center]
    71 |}
     63
     64[[Image(https://devel.rtems.org/old_images/Cfi.png)]]
    7265
    7366'''DDR SDRAM Memory Controller'''
    7467
    7568The Altera DDR SDRAM High Performance MegaCore function is used to interface to a PowerChip Semiconductor A2S56D40CTP-G5PP DDR SDRAM device, creating a video frame buffer, and Ethernet data transmit and receive buffer. The video data (RGB) is stored in the video frame buffer in unpacked 64-bit format. An SG-DMA is used to transfer the 64-bit-wide video stream from the memory into the video pipeline. The MegaCore function is configured to a 16-bit width clocked at 133 MHz. The local interface to the SG-DMA is configured to a 64-bit width clocked at 66.5 MHz and hence the memory controller is configured for half-rate operation.
    76 {|align="center"
    77 |-
    78 |[wiki:File:sdram1.png center]
    79 |}
     69
     70[[Image(https://devel.rtems.org/old_images/sdram1.png)]]
    8071
    8172'''SD/MMC SPI'''
     
    8879 *  Hardware assisted CRC calculation
    8980 *  Low level drivers included
    90 {|align="center"
    91 |-
    92 |[wiki:File:spi1.png center]
    93 |}
     81
     82[[Image(https://devel.rtems.org/old_images/spi1.png)]]
     83
    9484= Block diagram =
    9585
    96 {|align="center"
    97 |+'''Block diagram'''
    98 |-
    99 |[wiki:File:Niosblock.png center]
    100 |}
     86[[Image(https://devel.rtems.org/old_images/Niosblock.png)]]
     87
    10188= References =
    102 
    103 
    104 http://www.altera.com/literature/hb/nios2/n2sw_nii52002.pdf
    105 
    106 http://www.altera.com/products/devkits/altera/kit-cyc3-embedded.html
    107 
    108 http://www.altera.com/literature/ds/ds_nios2_3c25_lcd.pdf
     89* http://www.altera.com/literature/hb/nios2/n2sw_nii52002.pdf
     90* http://www.altera.com/products/devkits/altera/kit-cyc3-embedded.html
     91* http://www.altera.com/literature/ds/ds_nios2_3c25_lcd.pdf