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Nios2_iss

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10	10	The Nios II processor runs at a frequency of 100 MHz and is connected to high performance DDR SDRAM memory, on-chip descriptor memory, and CFI flash memory. Clock crossing bridges are required between the Nios II processor and the DDR SDRAM memory and slow peripherals components because these components run in different clock regions. A pipeline bridge between the Nios II processor and the flash tri-state bridge to external flash component ensures system fMAX is not affected and that every master sees every slave at the same address.
	11	The DDR SDRAM memory runs at 133 MHz. The ddr_sdram memory controller runs at half rate at local interface with a 64-bit data width, connected to a 32-bit width Nios II data bus and a 64-bit width SG-DMA through clock crossing bridges.
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12	13	'''Processor type: Fast (Nios /f)'''