Context Navigation

Nios2_iss

v12	v13
8	8	= Processor =
9	9
	10	The Nios II processor runs at a frequency of 100 MHz and is connected to high performance DDR SDRAM memory, on-chip descriptor memory, and CFI flash memory. Clock crossing bridges are required between the Nios II processor and the DDR SDRAM memory and slow peripherals components because these components run in different clock regions. A pipeline bridge between the Nios II processor and the flash tri-state bridge to external flash component ensures system fMAX is not affected and that every master sees every slave at the same address.
10	11
11	12	'''Processor type: Fast (Nios /f)'''