Version 7 (modified by Gedare, on May 12, 2010 at 11:03:29 PM) (diff)

/* Overview */


<!-- When filling in the box,

+ Try to include links to other Wiki pages and websites. + If a field is not applicable, not setting the variable will result in it not being displayed + If Simulator is not set, then No. is displayed.


{{Infobox BSP |BSP_name = OpenSPARC T1 |Manufacturer = Sun Microsystems / OpenSparc? |image = ultrasparct1.jpg |caption = UltraSPARC T1 |Board_URL = |Architecture = SPARC-V9 |CPU_model = Niagara |Monitor = |Simulator = Yes. Simics, M5 |Aliases = |RAM = XXX MB |NVMEM = |Serial = |NICs = |Other = }}


Describe the board here. Include links to manuals, brochures, etc.

Niagara is a 64-bit SPARC processor conforming to the UltraSPARC Architecture 2005 specification of SPARC v9, which is referred to as sun4v. Architectures conforming to the original SPARC v9 are referred to as sun4u, which also includes the Joint Programming Specification (JPS) compliant processors.

This BSP is in development. Sources are available from the rtemssparc64 Google Code repository. This BSP is on target to merge during development of RTEMS 4.11, and a patch set is planned for independent release against 4.10.


UltraSPARC Architecture 2005 Specification

UltraSPARC T1 (TM) supplement to UltraSPARC Architecture 2005 Specification

Register ABI Compliance

Board Setup

If there are special jumper or ROM monitor settings, describe them.

Downloading and Executing

Describe the download procedure.


How do you debug code on this board? What gdb setup? BDM, stub, etc?

=Test Reports=