Version 20 (modified by Gedare, on Jun 17, 2010 at 8:42:19 PM) (diff)

/* Simics */


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{{Infobox BSP |BSP_name = OpenSPARC T1 |Manufacturer = Sun Microsystems / OpenSparc? |image = ultrasparct1.jpg |caption = UltraSPARC T1 |Board_URL = |Architecture = SPARC-V9 |CPU_model = Niagara |Monitor = |Simulator = Yes. Simics, M5 |Aliases = |RAM = XXX MB |NVMEM = |Serial = |NICs = |Other = }}


Describe the board here. Include links to manuals, brochures, etc.

Niagara is a 64-bit SPARC processor conforming to the UltraSPARC Architecture 2005 specification of SPARC v9, which is referred to as sun4v. Architectures conforming to the original SPARC v9 are referred to as sun4u, which also includes the Joint Programming Specification (JPS) compliant processors.

This BSP is in development, and is currently in "alpha" stage. Sources are available from the rtemssparc64 Google Code repository. The development directory is rtems/rtemscvs, and there is an archived version under rtems/rtems-sparc64. There is currently no release available for this BSP. This BSP is on target to merge during development of RTEMS 4.11, and a "beta" patch set is planned for independent release for RTEMS 4.10.


UltraSPARC Architecture 2005 Specification

UltraSPARC T1 (TM) supplement to UltraSPARC Architecture 2005 Specification

Register ABI Compliance

Board Setup

If there are special jumper or ROM monitor settings, describe them.

Downloading and Executing

Describe the download procedure.


Development of this BSP has been exclusively on simulators. There is no current documentation for using this BSP with real hardware.


Simics is a commercially licensed simulator. These instructions assume you can set up and run Simics independently and have the proper licenses. For a free simulator, try M5 as described below.

Follow the instructions provided with Simics for the Niagara target. You will need to download and extract the OpenSparc architecture and performance modeling tools.

Bundle RTEMS executables and SILO on to a bootable ISO9660 filesystem. rtemssparc64 has some scripts to help create the bootable disk. More details on how to do this will be forthcoming.


Follow the instructions on the M5 wiki for getting started. The examples given are for the Alpha targets. You will also want to compile and install the m5term application.

To build the sparc full system targets, use:

$ scons build/SPARC_FS/m5.debug $ scons build/SPARC_FS/m5.opt $ scons build/SPARC_FS/ $ scons build/SPARC_FS/

Download and extract the OpenSparc architecture and performance modeling tools. Copy *.bin and nvram1 from OpenSPARCT1_Arch.1.5/S10image/ to the /dist/m5/system/binaries/ directory. Also copy disk.s10hw2 from the S10image/ directory to the /dist/m5/system/disks/ directory. Rename reset.bin, q.bin, and openboot.bin to reset_new.bin, q_new.bin, and openboot_new.bin, which are the binaries expected by the m5 SPARC_FS scripts.

In a terminal window, start the simulator with:

$ build/SPARC_FS/m5.debug -d /tmp/output configs/example/

In another terminal, connect to the simulator with:

$ m5term localhost 3457

You should eventually see this in your m5term window:

m5 slave terminal: Terminal 0

Sun Fire T2000, No Keyboard Copyright 2005 Sun Microsystems, Inc. All rights reserved. OpenBoot? 4.20.0, 256 MB memory available, Serial #1122867. [mo23723 obp4.20.0 #0] Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.


The "ok" prompt is the OpenBoot? prompt. Just type boot and press enter, and the OpenSparc? Solaris image will start to boot.

The sparc64 sun4v BSP will boot on the SPARC_FS full system simulator of M5. The first step is to bundle RTEMS executables and SILO on to a bootable ISO9660 filesystem. rtemssparc64 has some scripts to help create the bootable disk, which uses the same approach for booting RTEMS on Simics Niagara. Next change the ${m5}/configs/common/ file and replace disk('disk.s10hw2') with disk('image.iso'), where image.iso is the ISO9660 filesystem image built for booting RTEMS. M5 will look in /dist/m5/system/disks for the image.iso file, so link image.iso to the /dist/m5/system/disks/image.iso location. For more details on using RTEMS with M5 see this blog.


This BSP is debugged using Simics. M5 full system simulation supports using GDB as a remote debugger, but it has not been successfully used with RTEMS yet.

=Test Reports=