Version 1 (modified by Apd2004, on Nov 24, 2011 at 7:44:24 PM) (diff)

Created page with "{{Infobox BSP |BSP_name = Mpc5566evb |Manufacturer = Freescale |image = |Board_URL = [ FreeScale?..."

Mpc5566evb (add page and link on mpc55xxevb)

{{Infobox BSP |BSP_name = Mpc5566evb |Manufacturer = Freescale |image = |Board_URL = FreeScale |Architecture = Power Architecture® |CPU_model = The Freescale e200z6 core |Simulator = Yes. Skyeye |RAM = 32 KB of cache (with line-locking) that can be configured as additional RAM |NVMEM = Flash : up to 3 MB + 32KB of cache |Serial = 2 * DSPI, 4 * SCI |Other = User Guide }}


  • The Freescale e200z6 core
  • High-performance 132 MHz 32-bit core with variable length encoding (VLE) built on Power Architecture technology
  • Single instruction multiple data (SIMD) module for DSP and floating point capabilities


  • 1 MB of embedded flash memory with error correction coding (ECC) and read while write (RWW) capability
  • Flash: Up to 3 MB
  • 32 KB of cache (with line-locking) that can be configured as additional RAM


  • High-speed sensor interface
  • Integrated FlexRay? controller
  • Crossbar architecture for efficient data flow
  • 32-channel enhanced direct memory access controller with advance scatter/gather
  • Interrupt controller capable of handling 281 selectable-priority interrupt sources
  • Frequency modulated phase-locked loop to assist in electromagnetic interference management
  • Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities
  • 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
  • 324-pin plastic ball grid array (PBGA) package
  • Temperature range: -40ºC to +125ºC


  • 20-channel dual enhanced queued analog-to-digital converter—up to 12-bit resolution and up to 1.25 ms conversions, six queues with triggering and DMA support
  • Two deserial serial peripheral interface (DSPI) modules—16 bits wide and up to six chip selects each
  • Two FlexCAN modules compatible with TouCAN
  • Four enhanced serial communication interface (eSCI) modules
  • 24-channel enhanced multiple I/O system with unified channels