= Mpc5566evb (add page and link on mpc55xxevb) =


{{Infobox BSP
|BSP_name     = Mpc5566evb
|Manufacturer = Freescale
|image        = MPC5566_BD.jpg?
|Board_URL = [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5566 FreeScale]
|Architecture = [http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=0162468rH3bTdG Power Architecture®]
|CPU_model    = The Freescale e200z6 core
|Simulator = Yes. [wiki:Developer/Simulators/SkyEye  Skyeye]
|RAM = 32 KB of cache (with line-locking) that can be configured as additional RAM
|NVMEM  = Flash : up to 3 MB + 32KB of cache
|Serial = CAN, SCI, SP
|Other = [http://www.freescale.com/files/32bit/doc/data_sheet/MPC5566.pdf?pspll=1 User Guide]
}}

= Features =


 * High-performance 132 MHz 32-bit Power Architecture technology core with variable length encoding (VLE)
 * Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
 * SPE (signal processing extension): DSP, SIMD and floating point capabilities
= Memory =


 * 3 MB of embedded flash memory with error correction coding (ECC) and RWW
 * 128 KB on-chip static RAM with ECC
 * 32 KB of cache (with line-locking) that can be configured as additional RAM
= System =


 * Two enhanced time processor units (eTPUs), each with 32 I/O channels and 24 KB of designated SRAM
 * 64-channel eDMA (enhanced direct memory access) controller
 * Interrupt controller (INTC) capable of handling 339 selectable-priority interrupt sources
 * Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
 * MPC500 compatible external bus interface
 * Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities > 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
 * 416-pin PBGA package
 * Temperature range: -40 to 125ºC
= I/O =


 * 40-channel dual enhanced queued analog-to-digital converters (eQADC)—each up to 12 bit resolution and up to 1.25 us conversions, six queues with triggering and DMA support
 * Four deserial serial peripheral interface (DSPI) modules—16 bits wide up to six chip selects each
 * Four controller area network (CAN) modules with 64 buffers each
 * Two enhanced serial communication interface (eSCI) modules
 * 24-channel enhanced multiple I/O system (EMIOS) with unified channels