Changes between Version 3 and Version 4 of TBR/BSP/Mpc5566evb_(add_page_and_link_on_mpc55xxevb)


Ignore:
Timestamp:
Nov 26, 2011, 11:56:58 PM (8 years ago)
Author:
Apd2004
Comment:

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  • TBR/BSP/Mpc5566evb_(add_page_and_link_on_mpc55xxevb)

    v3 v4  
    99|Architecture = [http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=0162468rH3bTdG Power Architecture®]
    1010|CPU_model    = The Freescale e200z6 core
    11 |Simulator = Yes. [wiki:Developer/Simulators/SkyEye  Skyeye]
    12 |RAM = 32 KB of cache (with line-locking) that can be configured as additional RAM
     11|Simulator =
     12|RAM = 128 KB + 32 KB of cache (with line-locking) that can be configured as additional RAM
    1313|NVMEM  = Flash : up to 3 MB + 32KB of cache
    1414|Serial = CAN, SCI, SP