Changes between Version 2 and Version 3 of TBR/BSP/Mpc5566evb_(add_page_and_link_on_mpc55xxevb)


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Timestamp:
Nov 26, 2011, 11:38:54 PM (8 years ago)
Author:
Apd2004
Comment:

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  • TBR/BSP/Mpc5566evb_(add_page_and_link_on_mpc55xxevb)

    v2 v3  
    55|BSP_name     = Mpc5566evb
    66|Manufacturer = Freescale
    7 |image        = Freescale_MPC5561.gif
    8 |Board_URL = [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5561 FreeScale]
     7|image        = MPC5566_BD.jpg?
     8|Board_URL = [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5566 FreeScale]
    99|Architecture = [http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=0162468rH3bTdG Power Architecture®]
    1010|CPU_model    = The Freescale e200z6 core
     
    1212|RAM = 32 KB of cache (with line-locking) that can be configured as additional RAM
    1313|NVMEM  = Flash : up to 3 MB + 32KB of cache
    14 |Serial = 2 * DSPI, 4 * SCI
     14|Serial = CAN, SCI, SP
    1515|Other = [http://www.freescale.com/files/32bit/doc/data_sheet/MPC5566.pdf?pspll=1 User Guide]
    1616}}
     
    1919
    2020
    21  * The Freescale e200z6 core
    22  * High-performance 132 MHz 32-bit core with variable length encoding (VLE) built on Power Architecture technology
    23  * Single instruction multiple data (SIMD) module for DSP and floating point capabilities
     21 * High-performance 132 MHz 32-bit Power Architecture technology core with variable length encoding (VLE)
     22 * Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
     23 * SPE (signal processing extension): DSP, SIMD and floating point capabilities
    2424= Memory =
    2525
    2626
    27  * 1 MB of embedded flash memory with error correction coding (ECC) and read while write (RWW) capability
    28  * Flash: Up to 3 MB
     27 * 3 MB of embedded flash memory with error correction coding (ECC) and RWW
     28 * 128 KB on-chip static RAM with ECC
    2929 * 32 KB of cache (with line-locking) that can be configured as additional RAM
    3030= System =
    3131
    3232
    33  * High-speed sensor interface
    34  * Integrated FlexRay controller
    35  * Crossbar architecture for efficient data flow
    36  * 32-channel enhanced direct memory access controller with advance scatter/gather
    37  * Interrupt controller capable of handling 281 selectable-priority interrupt sources
    38  * Frequency modulated phase-locked loop to assist in electromagnetic interference management
    39  * Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities
    40  * 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
    41  * 324-pin plastic ball grid array (PBGA) package
    42  * Temperature range: -40ºC to +125ºC
     33 * Two enhanced time processor units (eTPUs), each with 32 I/O channels and 24 KB of designated SRAM
     34 * 64-channel eDMA (enhanced direct memory access) controller
     35 * Interrupt controller (INTC) capable of handling 339 selectable-priority interrupt sources
     36 * Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
     37 * MPC500 compatible external bus interface
     38 * Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities > 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
     39 * 416-pin PBGA package
     40 * Temperature range: -40 to 125ºC
    4341= I/O =
    4442
    4543
    46  * 20-channel dual enhanced queued analog-to-digital converter—up to 12-bit resolution and up to 1.25 ms conversions, six queues with triggering and DMA support
    47  * Two deserial serial peripheral interface (DSPI) modules—16 bits wide and up to six chip selects each
    48  * Two FlexCAN modules compatible with TouCAN
    49  * Four enhanced serial communication interface (eSCI) modules
    50  * 24-channel enhanced multiple I/O system with unified channels
     44 * 40-channel dual enhanced queued analog-to-digital converters (eQADC)—each up to 12 bit resolution and up to 1.25 us conversions, six queues with triggering and DMA support
     45 * Four deserial serial peripheral interface (DSPI) modules—16 bits wide up to six chip selects each
     46 * Four controller area network (CAN) modules with 64 buffers each
     47 * Two enhanced serial communication interface (eSCI) modules
     48 * 24-channel enhanced multiple I/O system (EMIOS) with unified channels