Changes between Initial Version and Version 1 of TBR/BSP/Mpc5566evb_(add_page_and_link_on_mpc55xxevb)


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Timestamp:
Nov 24, 2011, 7:44:24 PM (8 years ago)
Author:
Apd2004
Comment:

Created page with "{{Infobox BSP |BSP_name = Mpc5566evb |Manufacturer = Freescale |image = |Board_URL = [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5561 FreeScale?..."

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  • TBR/BSP/Mpc5566evb_(add_page_and_link_on_mpc55xxevb)

    v1 v1  
     1= Mpc5566evb (add page and link on mpc55xxevb) =
     2
     3
     4{{Infobox BSP
     5|BSP_name     = Mpc5566evb
     6|Manufacturer = Freescale
     7|image        =
     8|Board_URL = [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5561 FreeScale]
     9|Architecture = [http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=0162468rH3bTdG Power Architecture®]
     10|CPU_model    = The Freescale e200z6 core
     11|Simulator = Yes. [wiki:Developer/Simulators/SkyEye  Skyeye]
     12|RAM = 32 KB of cache (with line-locking) that can be configured as additional RAM
     13|NVMEM  = Flash : up to 3 MB + 32KB of cache
     14|Serial = 2 * DSPI, 4 * SCI
     15|Other = [http://www.freescale.com/files/32bit/doc/data_sheet/MPC5566.pdf?pspll=1 User Guide]
     16}}
     17
     18= Features =
     19
     20
     21 * The Freescale e200z6 core
     22 * High-performance 132 MHz 32-bit core with variable length encoding (VLE) built on Power Architecture technology
     23 * Single instruction multiple data (SIMD) module for DSP and floating point capabilities
     24= Memory =
     25
     26
     27 * 1 MB of embedded flash memory with error correction coding (ECC) and read while write (RWW) capability
     28 * Flash: Up to 3 MB
     29 * 32 KB of cache (with line-locking) that can be configured as additional RAM
     30= System =
     31
     32
     33 * High-speed sensor interface
     34 * Integrated FlexRay controller
     35 * Crossbar architecture for efficient data flow
     36 * 32-channel enhanced direct memory access controller with advance scatter/gather
     37 * Interrupt controller capable of handling 281 selectable-priority interrupt sources
     38 * Frequency modulated phase-locked loop to assist in electromagnetic interference management
     39 * Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities
     40 * 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
     41 * 324-pin plastic ball grid array (PBGA) package
     42 * Temperature range: -40ºC to +125ºC
     43= I/O =
     44
     45
     46 * 20-channel dual enhanced queued analog-to-digital converter—up to 12-bit resolution and up to 1.25 ms conversions, six queues with triggering and DMA support
     47 * Two deserial serial peripheral interface (DSPI) modules—16 bits wide and up to six chip selects each
     48 * Two FlexCAN modules compatible with TouCAN
     49 * Four enhanced serial communication interface (eSCI) modules
     50 * 24-channel enhanced multiple I/O system with unified channels