wiki:TBR/BSP/Mcp750

Mcp750

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{{Infobox BSP |BSP_name = mcp750 |Manufacturer = Motorola |image = Mcp75012.jpg |caption = |Board_URL = http://www.motorola.com |Architecture = PowerPlus? 128-bit, 2 way interleaved |CPU_model = 233/366/466 MHz MPC750 |Monitor = |Simulator = No. |RAM = 16 to 256MB of ECC DRAM |NVMEM = Up to 9MB on-board Flash memory |Serial = Two USB ports, Two async serial ports, two async/sync serial ports }}

Overview

The MCP750 series is a family of PowerPC microprocessor-based CompactPCI host-slot processor modules. Benefiting from Motorola’s PowerPlus? Architecture, the MCP750 series pushes performance and func- tionality to unprecedented levels.

Utilizing Motorola’s low-power, high-performance PowerPC 750 microproces- sors with 1MB of secondary cache, the peripheral component interconnect (PCI) bus for the on-board peripherals, processor/memory bus to PCI bus bridge, and a 64-bit bridge to the CompactPCI interface, the MCP750 packs optimum performance and functionality in just a single CompactPCI slot.

Board Setup

Power Requirements:

(not including power required by PMC or SIMs)

+3.3V ±5% +5V ±5%

MCP750-1242: 1.9 A typ. 3.8 A typ.

2.5 A max. 4.4 A max.

with TMCP700-001: 1.9 A typ. 4.0 A typ.

2.5 A max. 4.8 A max.

Equipment Required:

The following equipment is required to complete an MCP750 system:

  • CompactPCI system enclosure
  • System console terminal
  • Operating system (and/or application software)
  • Disk drives (and/or other I/O) and controllers
  • Transition module (TMCP700) and connecting cables

MCP750 modules are factory configured for I/O handling via a TMCP700 transition module. There are various MCP750 models available that correspond to different memory configurations. One transition module supports all configurations of the board.

Features

The following table summarizes the features of the MCP750 single-board computers. Table 3-1. MCP750 Features Feature Description:

  • Microprocessor: MPC750 PowerPC processor (233 MHz, 366 MHz, or 450MHz)
  • ECC DRAM: 16MB-256MB on RAM300 module
  • L2 cache memory: Populated with 1MB on base board
  • Flash Memory: (4MB or 8MB 64-bit Flash) on RAM300 module
  • Real-time clock: 8KB NVRAM with RTC and battery backup (SGS-Thomson M48T559)
  • Switches: RESET and ABORT
  • Status: LEDs four: BFL, CPU, PCI, and CPCI
  • Interrupts Software: interrupt handling via Raven (PCI-MPU bridge) and Peripheral Bus Controller
  • Serial I/O: 1 async port (COM1) via front panel. 2 async ports, 2 sync/async ports via the transition module
  • Parallel I/O: IEEE 1284 bidirectional parallel port (PC87307 SIO) via the transition module
  • Ethernet I/O: 10/100 Base-T connection via the front panel
  • PCI interface: One IEEE P1386.1 PCI Mezzanine Card (PMC) slot; one 110 pin CompactPCI connector (J4) for PCIexpansion.
  • Keyboard/mouse: Support for keyboard and mouse input (PC87307 SIO) via the transition

interface module

  • Floppy disk: Support for floppy disk drive (PC87307 SIO) via the transition module

controller

  • CompactPCI: 33MHz, 64-bit CompactPCI interface with DEC 21154 PCI-to-PCI bridge.
  • USB: I/O USB Host/Hub? interface with two ports routed to the front panel or transition module
  • EIDE: Primary EIDE port routed to onboard Compact FLASH connector. Secondary EIDE port routed to the transition module

Debugging

PPCBug Basics

The PowerPC debug firmware (PPCBug) is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation. The PPCBug provides a high degree of functionality, user friendliness, portability, and ease of maintenance. It is portable and easy to understand because it was written entirely in the C programming language, except where necessary to use assembler functions. The PPCBug includes commands for:

  • Display and modification of memory
  • Breakpoint and tracing capabilities
  • A powerful assembler and disassembler useful for patching programs
  • A self-test at power-up feature which verifies the integrity of the system

References

Last modified on Nov 29, 2010 at 10:22:58 PM Last modified on Nov 29, 2010, 10:22:58 PM