wiki:TBR/BSP/Mcf52235

Version 6 (modified by Richard Campbell, on Mar 26, 2011 at 12:42:54 AM) (diff)

/* Firmware Setup */ Added RTEMS Lab board settings

Mcf52235

{{Infobox BSP |BSP_name = MCF52235EVB |Manufacturer = Motorola |image = Motorola_MCF52235EVB.jpg |caption = Motorola MCF52235EVB design |Board_URL = ā€‹http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MCF5223X |Architecture = MCF5223X |CPU_model = V2 ColdFire? |Monitor = uBoot, uMon |Simulator = N/A |Aliases = No |RAM = 32KB SRAM |NVMEM = 256 KB Flash |Serial = RS232 serial port |NICs = Ethernet |Other = N/A }}

Overview

The MCF52235 represents a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire? microarchitecture. Featuring up to 32 Kbytes of internal SRAM and 256 Kbytes of flash memory, four 32-bit timers with DMA request capability, a 4-channel DMA controller, fast Ethernet controller, a CAN module, an I2Cā„¢ module, 3 UARTs and a queued SPI, the MC52235 family has been designed for general-purpose industrial control applications.

This 32-bit device is based on the Version 2 ColdFire? core operating at a frequency up to 60 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include up to 256 Kbytes of Flash and 32 Kbytes of static random access memory (SRAM).

This BSP was heavily based on the MCF5235? BSP.

Key Features

  • Version 2 ColdFire? variable-length RISC processor core
  • System debug support
  • On-chip memories
  • Power management
  • Fast Ethernet Controller (FEC)
  • On-chip Ethernet Transceiver (EPHY)
  • FlexCAN 2.0B module
  • Three universal asynchronous/synchronous receiver transmitters (UARTs)
  • I2C module
  • Queued serial peripheral interface (QSPI)
  • Fast analog-to-digital converter (ADC)
  • Four 32-bit DMA timers
  • Four-channel general purpose timers
  • Pulse-width modulation timer
  • Real-Time Clock (RTC)
  • Two periodic interrupt timers (PITs)
  • Software watchdog timer
  • Clock Generation Features
  • Dual Interrupt Controllers (INTC0/INTC1)
  • DMA controller
  • Reset
  • Chip integration module (CIM)
  • General purpose I/O interface
  • JTAG support for system level board testing

397px?

Board Setup

RTEMS Lab Board

Display the firmware settings using the boot monitor's "state" command:

INET> state
iface 0- IP addr:192.168.1.99  subnet:255.255.255.0  gateway:192.168.1.1
current tick count 4204
Task wakeups:netmain: 27
nettick: 2102
keyboard: 2099

Downloading and Executing

Describe the download procedure.

Debugging

How do you debug code on this board? What gdb setup? BDM, stub, etc?

=Test Reports=

=References=

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