Changes between Version 1 and Version 2 of TBR/BSP/Mbx821_002_(add_page_and_link_on_Mbx8xx_page)


Ignore:
Timestamp:
Nov 25, 2011, 11:35:43 PM (8 years ago)
Author:
Vladimir Stankulov
Comment:

/* Processor */

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  • TBR/BSP/Mbx821_002_(add_page_and_link_on_Mbx8xx_page)

    v1 v2  
    9797 *  Two serial management channels (SMCs)
    9898 *  A serial peripheral interface (SPI) channel
    99  *  an Interprocessor-Integrated Controller (I
    100 2
    101 C) channel for data
    102 exchanges between the MPC821 and other ICs with I
    103 2
    104 C
    105 capability — microcontrollers, LCD displays, real-time clock
    106 devices, etc.
    107 The MPC821’s memory controller supports all available types of
    108 memory. Its PCMCIA controller supports up to two PCMCIA
    109 sockets (one is implemented on the MBX). There is also a display
    110 capability via LCD controller and a real-time clock
    111 
     99 *  an Interprocessor-Integrated Controller channel for data exchanges between the MPC821 and other ICs with I2C capability — microcontrollers, LCD displays,real-time clock devices, etc.The MPC821’s memory controller supports all available types of memory. Its PCMCIA controller supports up to two PCMCIA sockets (one is implemented on the MBX). There is also a display capability via LCD controller and a real-time clock
    112100= Cooling Requirements =
    113101