wiki:TBR/BSP/MPC5674FEVB

Version 28 (modified by Mehr Mohammad Sachal, on Nov 3, 2018 at 5:13:58 AM) (diff)

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MPC5674FEVB

{{Infobox BSP |BSP_name = MPC5674FEVB |Manufacturer = Freescale |image = PhyCORE.jpg |CPU_model = e200z7 264MHz |RAM = 256K SRAM w/ECC |NVMEM = 4 MB of flash memory |Architecture = PowerPC |Serial = 3x eSCI, 4X DSPI |Board_URL = http://cache.freescale.com/files/32bit/doc/app_note/AN3903.pdf }}

Overview

Freescale MPC5674FEVB

The VertiCal? system is designed to enable the use of new enhanced automotive calibration and debug tools on the MPC5674F family of automotive microcontrollers. VertiCal? components are available to support a wide range of MPC5600 devices in various package types. All VertiCal? hardware is designed to support a standardized tool connector, allowing a variety of calibration and debug hardware to be connected and reused.

Features:

  • VertiCal? developement system compatible
  • Pitch 1.00 (mm)
  • Up to 516 Pins
  • Use 100% production silicon
  • Standardized hardware across the MPC5600 family
  • Interconnect standard supported by multiple calibration tool developers
  • Support for simplified implementation of overlay memory
  • Flexibility to support new microcontroller features for prototyping use
  • Allows system calibration w/o impacting standard MCU I/O resources
  • Uses tried and tested technology

Features and Benefits

Features and Benefits
No image "Freescale5674.png" attached to File

Core

The MPC5674F employs the e200z7 core, instead of the e200z6 core used on the MPC5566. The e200z7 core is instruction-set equivalent with the e200z6 core, however some new instructions and features are added to the e200z7. The essential differences in the two cores are described in the following bullets.

  • VLE — The MPC5674F provides several new VLE instructions that are designed to maximize performance when the core is saving and restoring context. Existing e200z6 VLE code will execute without modifications on the e200z7 core. Not all tool partners will support these new instructions initially.
  • MMU Entries — The number of MMU entries has been increased from 32 to 64 on the MPC5674F.

The MMU entries initialized by the BAM are unchanged, and existing code that relies on the BAM initialization will execute correctly.

  • Cache — The cache size remains 32 KB, however the architecture has been changed from a unified 32K type cache to a Harvard type cache, with 16 KB for data and 16 KB for instruction storage. Three new registers associated with the instruction cache block are added; L1CFG1, L1CSR1, and

LFINV1. Cache initialization code must be modified to include both blocks. The unified cache on existing e200z6 cores is initialized and locked using the data cache instructions, therefore code that puts the stack into the cache does not need to be modified.

  • Non-Maskable Interrupts (NMI) — The MPC5674F provides a new NMI that can be used to generate a non-maskable interrupt to the core. No software changes are required unless this new feature is to be used.
  • The Machine Check exception has been modified. Existing code for handling machine check must be modified to clear the machine check cause in the MCSR register. Refer to Freescale document e200z7RM, e200z7 PowerPC™ Core Reference Manual, for details.
  • SIMD — The MPC5674F employs the new SPE2 instruction set that provides expanded signal processing capability. SPE2 is a superset of the existing SPE library. Any existing SPE code does not require modification.

SRAM

The MPC5674F has 256 KB of SRAM, compared to the 128 KB of SRAM on the MPC5566. If the extra SRAM is to be used, the application initialization code must be modified so that it initializes all SRAM up to 256 KB. Additionally, any linker directive files must be updated to reflect the change in the memory map. The MPC5674F ECC supports single-bit error reporting for SRAM memory.

Flash

  • The MPC5674F has 4 MB of flash memory,1 increased from the 3 MB of flash memory on the MPC5566.
  • The MPC5674F requires a different flash-programming algorithm that will be provided by FSL as a software driver. Any proprietary flash-programming algorithms or drivers must be re-coded for the MPC5674F.
  • The MPC5674F ECC supports single-bit error reporting for flash memory.
  • There are now two sets of control registers, one for each flash array.
  • Any PC tools used for programming flash will need to be updated.

References

http://cache.freescale.com/files/32bit/doc/app_note/AN3903.pdf

http://www.scribd.com/doc/75934649/Datasheet

http://www.freescale.com/