wiki:TBR/BSP/M5484FireEngine

Version 2 (modified by Deivid, on Nov 29, 2011 at 2:51:21 AM) (diff)

M5484FireEngine

{{Infobox BSP |BSP_name = MCF548x |Manufacturer = ColdFire? |image = PhyCORE-MCF548x_Web_03.jpg |caption = PhyCORE-MCF548x |Board_URL = http://pdf1.alldatasheet.com/datasheet-pdf/view/184676/FREESCALE/mcf5485.html |Architecture = Freescale Coldfire |CPU_model = MCF548x |Monitor = uBoot, uMon |Simulator = N/A |Aliases = No |RAM = DDR SDRAM: 64 to 128 MB. |NVMEM = 32 MB Flash |Serial = Two RS-232 Serial Ports & Two TTL Serial Ports. |NICs = one. NIC part name. }}

http://pdf1.alldatasheet.com/datasheet-pdf/view/184676/FREESCALE/mcf5485.html

  • Limited superscalar V4 ColdFire? processor core
  • Double-precision conforms to IEE-754 standard
  • Controller Area Network (CAN) 2.0B Interface
  • 32-bit double data rate (DDR) synchronous DRAM

(SDRAM) controller – 66–133 MHz operation – Supports DDR and SDR DRAM – Built-in initialization and refresh – Up to four chip selects enabling up to one GB of external

  • 32-Kbyte system SRAM

– Arbitration mechanism shares bandwidth between internal bus masters

  • IrDA 1.1 interfaces
  • Up to four programmable serial controllers (PSCs) each

with separate 512-byte receive and transmit FIFOs for UART, USART, modem, codec

  • Debug and test features

ColdFire? background debug mode (BDM) port – JTAG/ IEEE 1149.1 test access port

  • Estimated power consumption

– Less than 1.5W (388 PBGA)