Changes between Version 1 and Version 2 of TBR/BSP/Lpc32xx

Timestamp:

11/27/10 21:54:04 (13 years ago)

Author:

ZumZoom

Comment:

TBR/BSP/Lpc32xx

@@ -3 +3 @@
 
 {{Infobox BSP
-|BSP_name     = lpc32xx
+|BSP_name     = lpc32x0
 |Manufacturer = NXP
-|image        = 
+|image        = Nxp ea lpc3250 kit.jpg
 |caption      =
 
-|Board_URL    = http://www.lpctools.com/phycore-arm9lpc3250.aspx
+|Board_URL    = [http://www.rtems.org/wiki/index.php/Lpc32xx#References References]
 |Architecture = ARMv5
-|CPU_model    = ARM7
+|CPU_model    = ARM9
 |Monitor      = U-Boot
-|Simulator    = 
-|Aliases      = Various
-|RAM          = Various
+|Simulator    = No
+|Aliases      = No
+|RAM          = 128/256 KB SRAM 
 |NVMEM        = Various
-|Serial       = Yes
-|NICs         = Yes.
-|Other        = Various
+|NICs         = Yes
 }}
+= Overview =
+
+
+Built around a 90-nm, 266MHz ARM926EJ-S CPU core and a Vector Floating Point (VFP) coprocessor, the NXP LPC32x0 family is designed for applications that require high performance, high integration, and low power consumption. The VFP coprocessor increases the speed of typical calculations by a factor of four to five in scalar mode, and much more in optimized vector mode. Advanced process technology optimizes each microcontroller's intrinsic power, and software-controlled features provide best-in-class power management.
+The LPC3240 and LPC3250 microcontrollers have a 10/100 Ethernet MAC with a dedicated DMA controller. On the LPC3230 and the LPC3250, there is also a flexible LCD controller that supports STN and TFT panels, and offers a dedicated DMA controller and programmable display resolution up to 1024 x 768 and up to 16M colors.
+Multiple interfaces for serial communications increase design flexibility, provide larger buffer size, and deliver higher processing power. Each LPC32x0 microcontroller has a 10-bit, 400-kHz A/D converter with three channels and a touchscreen interface. A seven-layer, 32-bit, 104-MHz AHB matrix provides a separate bus for each of the seven AHB masters (D-cache, I-cache, two DMA, Ethernet MAC, USB controller, and LCD controller). 
+= Key Features =
+
+
+ *  266MHz, 32-bit ARM9EJ-S core
+ *  Vector Floating Point coprocessor
+ *  Up to 256KB of internal SRAM and 32KB I-cache/32KB D-cache
+ *  External memory controller for DDR and SDR SDRAM, SRAM, and Flash
+ *  Available 10/100 Ethernet MAC
+ *  USB OTG with full-speed host and device capabilities
+ *  Available 24-bit LCD controller supports STN and TFT panels
+ *  Comprehensive set of serial interfaces
+ *  SD memory-card interface
+
+<table class="wikitable">
+<caption>Comparison table</caption>
+<tr><th>Product</th><th>SRAM(KB)</th><th>10/100 Ethernet</th><th>LCD controller</th><th>USB host, device, OTG</th><th>Package</th></tr>
+<tr><td>LPC3220</td><td>128</td><td>0</td><td>0</td><td>1</td><td>TFBGA296</td></tr>
+<tr><td>LPC3230</td><td>256</td><td>0</td><td>1</td><td>1</td><td>TFBGA296</td></tr>
+<tr><td>LPC3240</td><td>256</td><td>1</td><td>0</td><td>1</td><td>TFBGA296</td></tr>
+<tr><td>LPC3250</td><td>256</td><td>1</td><td>1</td><td>1</td><td>TFBGA296</td></tr>
+</table>
+
+[wiki:File:Lpc32x0.gif centre]
+= Board Setup =
+
+
+If there are special jumper or ROM monitor settings, describe them.
+= Downloading and Executing =
+
+
+Describe the download procedure.
+= Debugging =
+
+
+How do you debug code on this board?  What gdb setup?  BDM, stub, etc?
+= Test Reports =
+
+
+{{Test Report
+|Version = RTEMS Version
+|Date    = Date
+|User    = User
+|Report  = reports that something happened. 
+}}
+= References =
+
+
+[http://www.lpctools.com/phycore-arm9lpc3250.aspx lpctools.com]
+
+[http://ics.nxp.com/products/lpc3000/lpc32x0/ ics.nxp.com]
+
+{{Navbox_BSPs}}