wiki:TBR/BSP/LM3S6965

Version 8 (modified by Ivaylo, on Dec 17, 2011 at 5:58:03 AM) (diff)

/* Specifications */

LM3S6965

Overview

Stellaris Microcontroller LM3S6965

The Stellaris® LM3S6965 Evaluation Board is a compact and versatile evaluation platform for the Stellaris LM3S6965 ARM® Cortex™-M3-based microcontroller. The evaluation kit uses the LM3S6965 microcontroller’s fully integrated 10/100 Ethernet controller to demonstrate an embedded web server. You can use the board either as an evaluation platform or as a low-cost in-circuit debug interface(ICDI). In debug interface mode, the on-board microcontroller is bypassed, allowing programming or debugging of an external target. The kit is also compatible with high-performance external JTAG debuggers. This evaluation kit enables quick evaluation, prototype development, and creation of applicationspecific designs for Ethernet networks. The kit also includes extensive source-code examples,allowing you to start building C code applications quickly.

Specifications

Features of the LM3S6965 Microcontroller

  • 32-bit RISC performance using ARM® Cortex™-M3 v7M architecture
    • 50-MHz operation
    • Hardware-division and single-cycle-multiplication
    • Integrated Nested Vectored Interrupt Controller (NVIC)
    • 42 interrupt channels with eight priority levels
  • 256 KB single-cycle Flash
  • 64 KB single-cycle SRAM
  • Four general-purpose 32-bit timers
  • Integrated Ethernet MAC and PHY
  • Three fully programmable 16C550-type UARTs
  • Four 10-bit channels (inputs) when used as single-ended inputs

Processor

=Block diagram=

File:Diagram23.png?

==References==

http://www.ti.com/lit/ug/spmu029a/spmu029a.pdf

http://www.ti.com/lit/ds/symlink/lm3s6965.pdf