wiki:TBR/BSP/LM3S6965

Version 20 (modified by Ivaylo, on Dec 17, 2011 at 6:19:31 AM) (diff)

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LM3S6965

Overview

The heart of the EVB is a Stellaris LM3S6965 ARM Cortex-M3-based microcontroller. The LM3S6965 offers 256 KB Flash memory, 50-MHz operation, an Ethernet controller, and a wide range of peripherals. Refer to the LM3S6965 data sheet (order number DS-LM3S6965) for complete device details. The LM3S6965 microcontroller is factory programmed with a quickstart demo program. The quickstart program resides in the LM3S6965 on-chip Flash memory and runs each time power is applied, unless the quickstart has been replaced with a user program.

Stellaris Microcontroller LM3S6965

The Stellaris® LM3S6965 Evaluation Board is a compact and versatile evaluation platform for the Stellaris LM3S6965 ARM® Cortex™-M3-based microcontroller. The evaluation kit uses the LM3S6965 microcontroller’s fully integrated 10/100 Ethernet controller to demonstrate an embedded web server. You can use the board either as an evaluation platform or as a low-cost in-circuit debug interface(ICDI). In debug interface mode, the on-board microcontroller is bypassed, allowing programming or debugging of an external target. The kit is also compatible with high-performance external JTAG debuggers. This evaluation kit enables quick evaluation, prototype development, and creation of applicationspecific designs for Ethernet networks. The kit also includes extensive source-code examples,allowing you to start building C code applications quickly.

Features of the LM3S6965 Microcontroller

  • 32-bit RISC performance using ARM® Cortex™-M3 v7M architecture
    • 50-MHz operation
    • Hardware-division and single-cycle-multiplication
    • Integrated Nested Vectored Interrupt Controller (NVIC)
    • 42 interrupt channels with eight priority levels
  • 256 KB single-cycle Flash
  • 64 KB single-cycle SRAM
  • Four general-purpose 32-bit timers
  • Integrated Ethernet MAC and PHY
  • Three fully programmable 16C550-type UARTs
  • Four 10-bit channels (inputs) when used as single-ended inputs
  • 32-bit RISC performance using ARM® Cortex™-M3 v7M architecture
    • 50-MHz operation
    • Hardware-division and single-cycle-multiplication
    • Integrated Nested Vectored Interrupt Controller (NVIC)
    • 42 interrupt channels with eight priority levels
  • 256 KB single-cycle Flash
  • 64 KB single-cycle SRAM
  • Four general-purpose 32-bit timers
  • Integrated Ethernet MAC and PHY
  • Three fully programmable 16C550-type UARTs
  • Four 10-bit channels (inputs) when used as single-ended inputs

Processor

The Cortex-M3 Processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include:

  • Compact core.
  • Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.
  • Rapid application execution through Harvard architecture characterized by separate buses for instruction and data.
  • Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware.
  • Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
  • Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
  • Migration from the ARM7™ processor family for better performance and power efficiency.
  • Full-featured debug solution
    • Serial Wire JTAG Debug Port (SWJ-DP)
    • Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
    • Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,and system profiling
    • Instrumentation Trace Macrocell (ITM) for support of printf style debugging
    • Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
  • Optimized for single-cycle flash usage
  • Three sleep modes with clock gating for low power
  • Single-cycle multiply instruction and hardware divide
  • Atomic operations
  • ARM Thumb2 mixed 16-/32-bit instruction set
  • 1.25 DMIPS/MHz

The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control.

Ethernet

A key feature of the LM3S6965 microcontroller is its fully integrated Ethernet controller. Only a RJ45 jack with integrated magnetics and a few passive components are needed to complete the 10/100baseT interface. The RJ45 jack incorporates LEDs that indicate traffic and link status. These are automatically managed by on-chip microcontroller hardware. Alternatively, the LEDs can be software controlled by configuring those pins as general-purpose outputs. The LM3S6965 supports automatic MDI/MDI-X so the EVB can connect directly to a network or to another Ethernet device without requiring a cross-over cable.

Clocking

The LM3S6965 microcontroller has four on-chip oscillators, three are implemented on the EVB. A 8.0-MHz crystal completes the LM3S6965’s main internal clock circuit. An internal PLL, configured in software, multiples this clock to 50-MHz for core and peripheral timing. A small, 25-MHz crystal is used by the LM3S6965 microcontroller for Ethernet physical layer timing and is independent of the main oscillator.

Reset

The LM3S6965 microcontroller shares its external reset input with the OLED display. In the EVB,reset sources are gated through the CPLD, though in a typical application a simple wired-OR arrangement is sufficient. Reset is asserted (active low) under any one of three conditions:

  • Power-on reset
  • Reset push switch SW1 held down
  • Internal debug mode—By the USB device controller (U4 FT2232) when instructed by debugger

Power Supplies

The LM3S6965 is powered from a +3.3-V supply. A low drop-out (LDO) regulator regulates +5-V power from the USB cable to +3.3-V. +3.3-V power is available for powering external circuits. A +15-V rail is available when the OLED display is active. The speaker and OLED display boost-converter operate directly from the +5-V rail.

Debugging

Stellaris microcontrollers support programming and debugging using either JTAG or SWD. JTAG uses the signals TCK, TMS, TDI, and TDO. SWD requires fewer signals (SWCLK, SWDIO, and,optionally, SWO, for trace). The debugger determines which debug protocol is used.

Block diagram

File:Diagram34.png?

=References=

http://www.ti.com/lit/ug/spmu029a/spmu029a.pdf

http://www.ti.com/lit/ds/symlink/lm3s6965.pdf