wiki:TBR/BSP/Gumstix

Version 5 (modified by Mehr Mohammad Sachal, on Nov 7, 2018 at 5:41:05 AM) (diff)

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Gumstix

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BSP Infobox

BSP_namePXA270
ManufacturerGumstix
imageIntel pxa270.gif
captionPXA270
Board_URLhttp://www.legendmicro.com/Store/5836_INTEL-XSCALE-PXA270-PROCESSOR.lmsp,5836_INTEL-XSCALE-PXA270-PROCESSOR.lmsp
ArchitectureARM
CPU_model Intel PXA270
MonitoruBoot, uMon
SimulatorYes. Skyeye
AliasesBSP
RAM128 MB
NVMEM32 MB Flash, 16 KB EEPROM
Serial4 serial interfaces
Videohttp://www.engineeringtv.com/video/Dual-Core-Cortex-A9-Powers-The (or) http://www.youtube.com/watch?v=0DoZ-zi5JFU

Overview

The TRITON ETN/I SBC is a DIMM format module based on the new Intel XScale PXA255 cpu and includes Fast Ethernet and 4 serial interfaces onboard together with an additional 200 pin expansion interface.

TRITON-ETN/I is a complete computer, ingeniously implemented on a board smaller than a credit card, and ready to be designed into your embedded system. The ETN/I model includes a 400MHz Intel®XScale processor, SDRAM, Flash memory, Silicon ID and 100 Mbps Ethernet. It is possible to directly connect an LCD and PCMCIA / CF drive.

Despite these powerful features, the module occupies an area of just 67.6 x 36.6 mm and has a maximum height of only 7.3 mm is possible.

Board Setup

Board Features--Connex Benefits

Processor--PXA255 with Xscale (R) from Marvel (R)

20mm wide--fits into an exterior shell <1"

modular connector-- DF12C(3.0)60DS0.5V80 60-pin hirose connector; and 92-pin bus header

...logic level UARTs (3)--Put a transceiver off-board for RS232 level

... USB--client

...JTAG--access for lowest level debugging

...NSSP--DMA access

MMC/SD slot--available on netMMC expansion board

CF slot--available on cfstix and netCF expansion boards.

wireless--Bluetooth available on 400xm-bt motherboard

...--uses MMCX antenna connector for Bluetooth

...--each connex 400xm-bt motherboard comes with a Bluetooth antenna.

...--RoHS-compliant Infineon PBA31308 module - a Class 2 Bluetooth module included with each connex 400xm-bt

...--802.11g available via various 92-pin wifistix and wifistix-cf expansion boards

speed...--200Mhz, or400MHz

memory...--64MB SDRAM standard (100MHz);16MB in XM versions

configurable...--quick turnaround to drop SD, SDRAM, or increase SDRAM speed

low power...--draws <250 mA at 400MHz without Bluetooth

sleep mode...--draws <50 mA while waiting for input (not even sleep mode)

Toolchain 3.4.0...--complete access to open source software for porting

supply 3.6V-5.0V...--takes Li-Ion, Li-Polymer, 3-NiMH, standard 4.5V or 5.0V inputs

Operating system...--Linux kernel 2.6.10 in flash

...--u-boot - bootloader

...--Userspace includes: sshd apache bluetooth utilities and more

...--can access more storage via CF card (not provided) in cfstix and netCF

Dimensions...--80mm x 20mm x 5.9mm;Smaller than the Basix due to lack of MMC connector.

Temperatures...--commercial temperatures only

Weight...--weighs 8g (1/4 oz);less than TWO TEASPOONS of water

Downloading and Executing

Describe the download procedure.

Debugging

Looking for a low cost, high functionality JTAG solution for the PXA270? As of several weeks ago, the openocd project now works with the Intel/Marvell? PXA270 processor. There are a number of USB based JTAG debuggers available for under $100, so the cost is minimal. This article provides a brief overview of JTAG, suggestions for your hardware design, and how to use OpenOCD (Open On-chip-debugger) with the PXA270.

OpenOCD

Over the past 8 years, I've used a number of JTAG solutions for programming and debugging embedded processor systems. At the low end, there are JTAG solutions for flash programming only that just wiggle pins on a PC parallel port which in turn wiggle pins on the scan chain of the processor. This way of doing things works, but is very slow because you have to fabricate the bus cycles in software and clock the entire jtag chain just to change the state of one pin. The jtag tools from the openwince project on Sourceforge fall into this category.

More advanced JTAG tools use the debugging capability of a processor to speed up flash programming and add debugging features. This typically involves downloading a tiny bit of code into the cache or internal SRAM in the CPU. This bit of code then can receive blocks of data or instructions and run bus cycles directly through the memory controller in the device. This makes flash programming very fast as most of the work is being done by the CPU, instead of manually controlling CPU pins using a jtag chain.

In past years, there have been various attempts at creating an open source JTAG solution, but none of them have gotten very far. When I had a project that needed to get done quickly, I simply bought or upgraded a BDI2000 debugger -- which is an excellent tool. The OpenOCD project now provides much of the same functionality as a BDI2000, but as in the case of the PXA270, it sometimes takes some work to get it all working.

OpenOCD was created by Dominic Rath as part of a diploma thesis (http://openocd.berlios.de/web/). It provides support for a wide range of target processors and JTAG debuggers. OpenOCD includes functionality for On-Chip Debugging, In-System Programming, and Boundary-Scan Testing.

Hardware design considerations

Although openocd has worked with other Xscale parts for some time, functionality for the PXA270 has not worked until recently. The primary reason for this is the way the power supplies are sequenced in most PXA270 designs. There is one supply to the PXA270 that is always on (VCC_BATT). All of the other supplies are often kept off until reset to the processor is de-asserted and the SYS_EN and PWR_EN signals go active. Because of this, some special considerations need to be taken during the sequencing of the reset signals, and the setting of the hold_rst bit in the PXA270 DCSR register.

Make sure you power the JTAG connection (Pin #1 of your JTAG connector) with VCC_BATT or some power that is always active. If you power the JTAG connector with a power supply that is controlled by the SYS_EN or PWR_EN signal, then you will loose JTAG power during the connection process and things obviously will not work.

JTAG Debugger Hardware

Most of the JTAG debugger debuggers used with OpenOCD are based on the FTDI FT2232 USB chip. The debugger I used is the arm-usb-ocd device from Olimex. At a cost of $80, you can't afford not to have one.

Image

OpenOCD Installation

OpenOCD can use two different libraries that provide access to the FTDI chip: an open source library named libftdi, and a closed source library from FTDI named libftd2xx. I could not get the opensource libftdi library to work, so I suggest you use the FTDI library for now. Otherwise, installation is pretty straightforward. Find yourself a reasonably modern Linux computer and follow instructions on the following page: http://openfacts.berlios.de/index-en.phtml?title=Building_OpenOCD . Make sure you use the --enable-ft2232_ftd2xx option when running configure. On Ubuntu 7.04:

Install the FTDI library:

  • wget http://www.ftdichip.com/Drivers/D2XX/Linux/libftd2xx0.4.13.tar.gz
  • mkdir libftd2xx; cd libftd2xx; tar -xzf ../libftd2xx0.4.13.tar.gz
  • sudo cp *.h /usr/local/include/
  • sudo cp libftd2xx.so.0.4.13 /usr/local/lib
  • cd /usr/local/lib/; ln -s libftd2xx.so.0.4.13 libftd2xx.so; sudo ln -s libftd2xx.so.0.4.13 libftd2xx.so.0
  • cd /usr/lib; ln -s /usr/local/lib/libftd2xx.so.0.4.13 libftd2xx.so.0

Install OpenOCD:

  • sudo apt-get install build-essential
  • sudo apt-get install automake
  • sudo apt-get install autoconf
  • svn checkout svn://svn.berlios.de/openocd/trunk openocd
  • cd openocd
  • ./configure --enable-ft2232_ftd2xx
  • make
  • sudo make install

OpenOCD Configuration

OpenOCD is configured using a configuration file. An example is:

# config for Intel PXA270 # not, as of 2007-06-22, openocd only works with the # libftd2xx library from ftdi. libftdi does not work.

telnet_port 3333 gdb_port 4444

interface ft2232 ft2232_layout olimex-jtag ft2232_vid_pid 0x15BA 0x0003 ft2232_device_desc "Olimex OpenOCD JTAG" jtag_speed 0 # set jtag_nsrst_delay to the delay introduced by your reset circuit # the rest of the needed delays are built into the openocd program jtag_nsrst_delay 260 # set the jtag_ntrst_delay to the delay introduced by a reset circuit # the rest of the needed delays are built into the openocd program jtag_ntrst_delay 0

#use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst separate

#jtag scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) jtag_device 7 0x1 0x7f 0x7e

#target configuration daemon_startup reset

target xscale little reset_halt 0 pxa27x

# maps to PXA internal RAM. If you are using a PXA255 # you must initialize SDRAM or leave this option off working_area 0 0x5c000000 0x10000 nobackup

run_and_halt_time 0 30

#flash bank <driver> <base> <size> <chip_width> <bus_width> # works for P30 flash flash bank cfi 0x00000000 0x1000000 2 4 0

Programming Flash

After OpenOCD is installed, copy the above config file contents to a file name openocd.cfg, and run openocd in the same directory as your configuration file.

Currently, there is an issue in that the openocd is expecting a debug handler file at a specific relative path from the openocd binary. The easiest way to get around this for now is to to run openocd from the src directory in the openocd source code.

If you get the following message: Error: ft2232.c:1338 ft2232_init_ftd2xx(): unable to open ftdi device: 2, there is a permissions problem with the USB device. To get around this, run openocd using sudo, or add the appropriate rules to udev to allow the usb device to be used by any user.

OpenOCD runs as a daemon waiting for telnet or GDB connections. After openocd starts, you can connect to it by running the following command: telnet localhost 3333

At this point you should be presented with a OpenOCD prompt. The following is an example of how to program a bootloader into flash memory:

flash probe 0

flash 'cfi' found at 0x00000000

flash protect 0 0 5 off

cleared protection for sectors 0 through 5 on flash bank 0

flash erase 0 0 5 off

erased sectors 0 through 5 on flash bank 0 in 4s 615249us

flash write 0 /build/tmp/u-boot-holon.bin 0

wrote 121832 byte from file /build/tmp/u-boot-holon.bin to flash bank 0 at offset 0x00000000 in 6s 138592us (19.381735 kb/s)

Debugging

In this example, OpenOCD waits for GDB connections on port 4444. To debug code running on the target, you would use gdb in the same way you would use a BDI2000, or most any other hardware debugger with GDB.

Summary

OpenOCD is a robust, full-featured JTAG debug solution that supports many processors and low cost JTAG debuggers. There are still a few rough edges to clean up with PXA270 support, but OpenOCD is already a very useful tool for embedded software development.

Test Reports

{{Test Report |Version = iwmmxt optimization on PXA270 |Date = 23 Mar 2008 |User = Stanislav Brabec |Report = [http://lists.linuxtogo.org/pipermail/openembedded-devel/2008-April/005050.html reports }}]

Other

Industrial Temperature Specification

The TRITON-ETN/I operates from -45 degC to +85degC. It replaces the original ETN module that had 0..70 degC spec.

Marvell

Originally developed by Intel, the XScale product line was purchased by Marvell in 2006. Visit Marvell's XScale webpage

Expansion

The TRITON-ETN/I is supplied with a DIMM144 connector and two low-profile 100-pin SAMTEC connectors to provide the designer with access to most of the PXA255's signals for nearly unlimited expansion. See the Specifications below or download the datasheet for full connector pin-outs.

Low Power Consumption

The TRITON-ETN/I contains a Core Power Generator with more than 90% efficiency. Power consumption can be reduced by using a combination of sleep-mode and clock-rate selection:

  • Sleep Mode : only 20mA @ 3.3V
  • Maximum : 160mA to 250 mA @ 3.3V, depending on running processes

Prices and Configuration

Please contact us for latest prices. Different configurations are possible for volume orders - see datasheet.

TRITON Development Kit

The TRITON-ETN/I is compatible with the TRITON Development Kit-2.

Marvell® PXA270 with XScale™ Processor documentation

PXA270 Processor Developer's Manual

PXA270 Electrical, Mechanical, and Thermal Specifications

PXA270 Specification Update

PXA270 Processor Optimization Guide

PXA270 Design Guide

PXA270 Connecting NAND Flash

PXA270 Connecting to HD via VLIO

PXA270 Video Decoder Performance Optimization

PXA270 Smart LCD Panel

PXA270 Checklist