Changes between Version 4 and Version 5 of TBR/BSP/Gensh2


Ignore:
Timestamp:
Nov 7, 2018, 4:34:48 AM (11 months ago)
Author:
Mehr Mohammad Sachal
Comment:

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  • TBR/BSP/Gensh2

    v4 v5  
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    4 {{Infobox BSP
    5 |BSP_name     = Gensh2
    6 |Manufacturer = Hitachi Semiconductor
    7 |image        = sh-2.jpg
    8 |Board_URL    = http://www.hitachi.com/New/cnews/E/2001/0920/index.html
    9 |Architecture = 32-bit RISC architecture
    10 |CPU_model    = SH-2
    11 |Simulator    = Unspecified
    12 |Predecessor  = SH-1
    13 |RAM          = Unspecified
    14 |NVMEM        = Unspecified
    15 |Serial       = Unspecified
    16 |Operating Frequency = 80 MHz
    17 |Other        = Original Hitachi architecture
    18 32-bit internal data paths
    19 Five-stage pipeline
    20 }}= Overview =
     4= BSP Infobox =
     5||'''BSP_name'''||Gensh2||
     6||'''Manufacturer'''||Hitachi Semiconductor||
     7||'''image'''||sh-2.jpg||
     8||'''Board_URL'''||http://www.hitachi.com/New/cnews/E/2001/0920/index.html||
     9||'''Architecture'''||32-bit RISC architecture||
     10||'''CPU_model'''||SH-2||
     11||'''Simulator'''||Unspecified||
     12||'''Predecessor'''||SH-1||
     13||'''RAM'''||Unspecified||
     14||'''NVMEM'''||Unspecified||
     15||'''Serial'''||Unspecified||
     16||'''Operating Frequency'''||80 MHz||
     17||'''Other'''||Original Hitachi architecture 32-bit internal data paths Five-stage pipeline||
     18
     19= Overview =
    2120
    2221The SH2 was first manufactured in October 1993. The die size is 7.59mm by 7.44mm with an .8 micron die process. For comparison, modern CPUs are measured in nanometers. One nanometer is 1/1000 the size of one micron. The CPU chip size is 5.45mm².The SH-2 is a 32-bit RISC architecture, it has 16 general purpose registers, which makes it well suited for programs written in C[citation needed].It has a 16-bit fixed length instructions for high code density, features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.The SH-2 has a cache on all ROM-less devices.It also provides a vector-base-register, global-base-register and a procedure register.Today the SH-2 family stretches from 32k of on board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.The Hitachi SH2 processor is a custom-built, reduced instruction set computer architecture that belongs to the "Super-H" series. It was developed for embedded systems, such as motion-controlled robots, automobile engine control units and most notably, for the "Sega Saturn" gaming console. The main difference between the SH2 and the SH1 is that the SH2 has a cache.