Changes between Initial Version and Version 2 of TBR/BSP/Gensh2

Jan 7, 2013, 8:55:30 PM (7 years ago)


  • TBR/BSP/Gensh2

    v1 v2  
     1= Gensh2 =
     4{{Infobox BSP
     5|BSP_name     = Gensh2
     6|Manufacturer = Hitachi Semiconductor
     7|image        =
     9|Board_URL    =
     10|Architecture = 32-bit RISC architecture
     11|CPU_model    = SH-2
     12|Simulator    = Unspecified
     13|Predecessor  = SH-1
     14|RAM          = Unspecified
     15|NVMEM        = Unspecified
     16|Serial       = Unspecified
     17|Operating Frequency = 80 MHz
     18|Other        = Original Hitachi architecture
     1932-bit internal data paths
     20Five-stage pipeline
     21}}= Overview =
     23The SH2 was first manufactured in October 1993. The die size is 7.59mm by 7.44mm with an .8 micron die process. For comparison, modern CPUs are measured in nanometers. One nanometer is 1/1000 the size of one micron. The CPU chip size is 5.45mm².The SH-2 is a 32-bit RISC architecture, it has 16 general purpose registers, which makes it well suited for programs written in C[citation needed].It has a 16-bit fixed length instructions for high code density, features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.The SH-2 has a cache on all ROM-less devices.It also provides a vector-base-register, global-base-register and a procedure register.Today the SH-2 family stretches from 32k of on board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.The Hitachi SH2 processor is a custom-built, reduced instruction set computer architecture that belongs to the "Super-H" series. It was developed for embedded systems, such as motion-controlled robots, automobile engine control units and most notably, for the "Sega Saturn" gaming console. The main difference between the SH2 and the SH1 is that the SH2 has a cache.
     25Read more: Specs on Hitachi SH2 Processors | Functionality =
     27This chip directly supports the popular memory interface types, such as SDRAM, DRAM and Masked ROM. It includes a 32-bit fixed point multiplier and division unit for 3D calculations. The SH2 can be configured to support a dual-processor.
     29= Power Consumption =
     31SH2 processors consume 400MHz at 5 volts. The operating voltage range can be between 2.7 volts to 5.5 volts. The clock frequency is 28.7MHz for a CPU throughput of 25 million instructions per second.
     32= Architecture =
     34This processor has a 32-bit architecture, with 16 fixed length instructions and 16 general purpose registers, making it ideal for "C" language programming. The earliest SH2 had 4 kilobytes of cache for code pre-fetching. More advanced processors in the family had up to 32KB.
     35= Features =
     37<br />
     38 * '''Architecture:'''
     39•Original Hitachi architecture
     40<br />
     41•32-bit internal data paths
     43<br />
     44 * '''General-register machine:'''
     45•Sixteen 32-bit general registers
     46<br />
     47•Three 32-bit control registers
     48<br />
     49•Four 32-bit system registers
     51<br />
     52 * '''Instruction set Instruction length:'''
     53•16-bit fixed length for improved code efficiency
     54<br />
     55•Load-store architecture (basic arithmetic and logic operations areexecuted between registers)
     56<br />
     57•Delayed branch system used for reduced pipeline disruption
     58<br />
     59•Instruction set optimized for C language
     61<br />
     62 * '''Instruction execution time:'''
     63•One instruction/cycle for basic instructions
     65<br />
     66 * '''Address space:'''
     67•Architecture makes 4 Gbytes available
     69<br />
     70 * '''On-chip multiplier(SH-2 CPU):'''
     71•Multiplication operations executed in 1 to 2 cycles (16 bits × 16 bits? 32 bits) or 2 to 4 cycles (32 bits × 32 bits ? 64 bits), and
     72multiplication/accumulation operations executed in 3/(2)*cycles (16bits × 16 bits + 64 bits ? 64 bits) or 3/(2 to 4)* cycles (32
     73bits × 32bits + 64 bits ? 64 bits)
     75<br />
     76 * '''Pipeline:'''
     77•Five-stage pipeline
     79<br />
     80 * '''Processing states:'''
     81•Reset state
     82<br />
     83•Exception processing state
     84<br />
     85•Program execution state
     86<br />
     87•Power-down state
     88<br />
     89•Bus release state
     91<br />
     92 * '''Power-down states:'''
     93•Sleep mode
     94<br />
     95•Standby mode
     96<br />
     97Note:The normal minimum number of execution cycles (The number in parentheses in the
     98mumber in contention with preceding/following instructions).
     101=  References  =