| 34 | | * Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address Lines |
| 35 | | * Complete static design (0-33 MHz Operation) |
| 36 | | * Slave mode to disable CPU32+ (allows use with external processors) |
| 37 | | o Multiple QUICCs can share one system bus (one master) |
| 38 | | o MC68040 companion mode allows QUICC to be an MC68040 companion chip and intelligent peripheral (29 MIPS at 33 MHz) |
| 39 | | o All QUICC features available in slave mode |
| 40 | | * Memory controller (eight banks) |
| 41 | | o Contains complete Dynamic Random-Access Memory (DRAM) controller |
| 42 | | o Glueless interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random-Access Memory (SRAM), |
| 43 | | o Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc. |
| 44 | | o Boot chip select available at Reset (options for 8-, 16-, or 32-bit memory) |
| 45 | | o Special features for MC68040 including Burst Mode |
| 46 | | * Four general-purpose timers |
| 47 | | o Four 16-bit timers or two 32-bit timers |
| 48 | | * Two Independent DMAs (IDMAs) |
| 49 | | * System Integration Module (SIM60) |
| 50 | | o Bus monitor |
| 51 | | o Breakpoint logic provides on-chip H/W breakpoints |
| 52 | | o Spurious interrupt monitor |
| 53 | | o External masters may use on-chip features such as chip selects |
| | 34 | * Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address Lines |
| | 35 | * Complete static design (0-33 MHz Operation) |
| | 36 | * Slave mode to disable CPU32+ (allows use with external processors) |
| | 37 | * Multiple QUICCs can share one system bus (one master) |
| | 38 | * MC68040 companion mode allows QUICC to be an MC68040 companion chip and intelligent peripheral (29 MIPS at 33 MHz) |
| | 39 | * All QUICC features available in slave mode |
| | 40 | * Memory controller (eight banks) |
| | 41 | * Contains complete Dynamic Random-Access Memory (DRAM) controller |
| | 42 | * Glueless interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random-Access Memory (SRAM), |
| | 43 | * Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc. |
| | 44 | * Boot chip select available at Reset (options for 8-, 16-, or 32-bit memory) |
| | 45 | * Special features for MC68040 including Burst Mode |
| | 46 | * Four general-purpose timers |
| | 47 | * Four 16-bit timers or two 32-bit timers |
| | 48 | * Two Independent DMAs (IDMAs) |
| | 49 | * System Integration Module (SIM60) |
| | 50 | * Bus monitor |
| | 51 | * Breakpoint logic provides on-chip H/W breakpoints |
| | 52 | * Spurious interrupt monitor |
| | 53 | * External masters may use on-chip features such as chip selects |
| 63 | | * Many new commands (e.g., Graceful Stop Transmit, Close RxBD) |
| 64 | | * Supports continuos mode transmission and reception on all serial channels |
| 65 | | * 2.5 kbytes of dual-port RAM |
| 66 | | * 14 Serial DMA (SDMA) channels |
| 67 | | * Three parallel I/O registers with open-drain capability |
| 68 | | * Each serial channel can have its own Pins (NMSI mode) |
| | 63 | * Many new commands (e.g., Graceful Stop Transmit, Close RxBD) |
| | 64 | * Supports continuos mode transmission and reception on all serial channels |
| | 65 | * 2.5 kbytes of dual-port RAM |
| | 66 | * 14 Serial DMA (SDMA) channels |
| | 67 | * Three parallel I/O registers with open-drain capability |
| | 68 | * Each serial channel can have its own Pins (NMSI mode) |
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