wiki:TBR/BSP/Gen68360

Gen68360

{{Infobox BSP |BSP_name = MC68360 |Manufacturer = Freescale Semiconductors |Reference = http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC68360 |Architecture = M68K |CPU Model = CPU+ Processor (8.3 MIPS at 33MHz) |Monitor = uBoot |Runs on Simulator? = No |Aliases = gen68360_040, pgh360 |RAM = 2.5 kbytes of dual-port RAM |Non-volatile Memory = 32 MB Flash, 16 KB EEPROM |Serial Ports = 3 highly configurable sync/async serial ports |Video = http://www.youtube.com/watch?v=EWzjpEwAod4 }}= Overview =

The MC68360 Quad Integrated Communication Controller (QUICC™) is a versatile one-chip integrated microprocessor and peripheral combination family that can be used in a variety of controller applications.

The MC68360 particularly excels in communications activities. The QUICC can be described as a next-generation MC68302, with higher performance in all areas of device operation, increased flexibility, and higher integration. The term "quad" comes from the fact that there are four serial communications controllers (SCCs) on the device. However, there are actually seven serial channels which include four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).

Features

CPU+ Processor (8.3 MIPS at 33MHz)

  • 32-bit version of the CPU32 core (fully compatible with CPU32)
  • Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address Lines
  • Complete static design (0-33 MHz Operation)
  • Slave mode to disable CPU32+ (allows use with external processors)
    • Multiple QUICCs can share one system bus (one master)
    • MC68040 companion mode allows QUICC to be an MC68040 companion chip and intelligent peripheral (29 MIPS at 33 MHz)
    • All QUICC features available in slave mode
  • Memory controller (eight banks)
    • Contains complete Dynamic Random-Access Memory (DRAM) controller
    • Glueless interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random-Access Memory (SRAM),
    • Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc.
    • Boot chip select available at Reset (options for 8-, 16-, or 32-bit memory)
    • Special features for MC68040 including Burst Mode
  • Four general-purpose timers
    • Four 16-bit timers or two 32-bit timers
  • Two Independent DMAs (IDMAs)
  • System Integration Module (SIM60)
    • Bus monitor
    • Breakpoint logic provides on-chip H/W breakpoints
    • Spurious interrupt monitor
    • External masters may use on-chip features such as chip selects
  • Periodic interrupt timer
  • On-chip bus arbitration with no overhead for internal masters
  • Low power stop mode
  • IEEE 1149.1 Test Access Port
  • RISC Communications Processor Module (CPM)
  • Many new commands (e.g., Graceful Stop Transmit, Close RxBD)
  • Supports continuos mode transmission and reception on all serial channels
  • 2.5 kbytes of dual-port RAM
  • 14 Serial DMA (SDMA) channels
  • Three parallel I/O registers with open-drain capability
  • Each serial channel can have its own Pins (NMSI mode)
  • Four baud rate generators
  • Four SCCs
  • Ethernet/IEEE 802.3 optional on SCCs 1-2@25 MHz, SCCs 1-3@33 MHz
  • HDLC Bus
  • Universal Asynchronous Receiver Transmitter (UART)
  • Synchronous UART
  • Asynchronous HDLC (RAM microcode option) to support PPP (Point to Point Protocol)
  • Two SMCs
  • UART
  • Transparent
  • General Circuit Interface (GCI) controller
  • One SPI
  • Time-Slot assignor
  • Supports two TDM channels
  • Parallel Interface Port (supports fast connection between QUICCs)= Board setup =

Host controlled setup

Required equipment:

  • +5 V 5 A power supply
  • +12 V 1 A power supply (optional)
  • Host Computer, one of the following:
    • Sun - 4 (SBus interface)
    • IBM-PC/XT/AT
  • ADI board - compatible with the host computer
  • 37 line flat cable with female 37 pin D-type connectors on each end

Stand alone setup

Required equipment:

  • +5 V 5 A power supply
  • +12 V 1 A power supply (optional)
  • VT100 compatible terminal
  • RS-232 cable with male 9 pin D-type connector on the QUADS side.

Debugging

BDM controller

The slave QUICC enables the M68360QUADS to become BDM controller to control other QUICC devices on the user application. The BDM feature enables the user to download code and provides hardware and software debugging capability of the user application. The 8 pin BDM connector P9 utilizes five pins of the slave QUICC port B. These pins are configured as general purpose I/O pins.

Ethernet controller

The slave QUICC provides Ethernet port for the M68360QUADS by connecting SCC1 to Motorola MC68160 EEST device (U35 in sheet 10). The MC68160 provides two Ethernet interfaces, twisted-pair on P8 and AUI on P7. The LEDs LD3-LD8 are controlled by the EEST, and they provide indications about the status of the Ethernet ports activity. The signals between the slave QUICC and the MC68160 appear on connector P10 for debugging purposes. P10 is a set of wire holes. The socket U24 is installed for internal factory testing only. For proper operation of the EEST, this socket must be empty.= References =

Last modified on Jan 6, 2013 at 7:15:09 PM Last modified on Jan 6, 2013, 7:15:09 PM