wiki:TBR/BSP/Gen68302

Gen68302

Infobox BSP

BSP_name Generic MC68302
Manufacturer Freescale Semiconductor Inc. / Motorola
image Freescale.jpg
Board_URL http://www.datasheetarchive.com/Indexer/Datasheet-082/DASF0048566.html
Architecture M68000
CPU_model MC68000/MC68008
RAM 1 MB
Serial 2. RS232
NICs None
NVMEM 32 MB Flash, 16 KB EEPROM

The gen68302 BSP is a BSP for a "generic mc68302" based system. Any board using this CPU should be able to use this BSP with only minor configuration changes.

Overview

The MC68302 integrated multiprotocol processor (IMP) is a very large-scale integration (VLSI) device incorporating the main building blocks needed for the design of a wide variety of controllers. The device is especially suitable to applications in the communications industry. The IMP is the first device to offer the benefits of a closely coupled, industry-standard M68000 microprocessor core and a flexible communications architecture. The IMP may be configured to support a number of popular industry interfaces, including those for the Integrated Services Digital Network (ISDN) basic rate and terminal adaptor applications. Concurrent operation of different protocols is easily achieved through a combination of architectural and programmable features. Data concentrators, line cards, modems, bridges, and gateways are examples of suitable applications for this device.

Features

Product Highlights

  • MC68000/MC68008 Microprocessor Core
  • Efficient architecture involves a separate RISC processor for handling communications
  • Three Serial Communications Controllers (SCCs)
  • Support for HDLC/SDLC, Bisync, UART, DDCMP, and Totally Transparent protocols.
  • Two Serial Management Controllers (SMCs) for IDL and GCI Channel.
  • Available at 16, 20, 25, and 33 MHz in three different Thin Quad Flat Pack Packages.
  • Strong 3rd Party tools support.

Typical Applications

  • ISDN equipment
  • Data Concentrators
  • Modems
  • Line Cards
  • Network Bridges
  • Gateways

Technical Specifications

  • MC68000/MC68008 Microprocessor Core (May be disabled to use the IMP as a peripheral)
  • SIB Including:
    • Independent Direct Memory Access (IDMA) Controller
    • Interrupt controller with two modes of operation
    • Parallel I/O ports, some with interrupt capability
    • On-Chip 1152-bytes of dual-port RAM
    • Three timers, with a software watchdog timer
    • Four programmable chip-select lines with wait-state logic
    • Programmable address mapping of dual-port RAM and IMP registers
    • On-Chip clock generator with an output clock signal
    • System Control
    • Bus arbitration logic with low interrupt latency support
    • System control register
    • Hardware watchdog for monitoring bus activity
    • Low power (Standby) modes
    • Disable CPU logic (M68000)
    • Freeze control for debugging selected on-chip peripherals
    • DRAM refresh controller
  • CP Including:
    • Main controller (RISC Processor)
    • Three full-duplex Serial Communication/Controllers? with the following protocols:
      • HDLC/SDLC
      • Bisync
      • UART
      • DDCMP
      • Totally Transparent
      • V.110
    • Six serial DMA channels dedicated to the three SOCs
    • Capability to send/receive up to eight buffers/frames without M68000 core intervention
    • Flexible physical interface accessible by SCCs for Inter-chip Digital Link (IDL), General Circuit Interface (GCI).
    • Pulse Code Modulation (PCM), and Non-multiplexed Serial Interface (NMSI) Operation.
    • Serial Communication Port (SCP) for synchronous communication.
    • Two Serial Management Controllers (SMCs) for IDL and GCI Channel.

Architecture

351px? In this architecture, the peripheral devices are isolated from the system bus through a dual-port memory. Various parameters and counters and all memory buffer descriptor tables reside in the dual-port RAM. The receive and transmit data buffers may be located in the on-chip RAM or in the off-chip system RAM. Six DMA channels are dedicated to the six serial ports (receive and trans- mit for each of the three SCC channels). If data for an SCC channel is programmed to be located in the external RAM, the CP will program the corresponding DMA channel for the required accesses, bypassing the dual-port RAM. If data resides in the dual-port RAM, then the CP accesses the RAM with one clock cycle and no arbitration delays.

NMSI comunications-oriented environment

When the interface to equipment or proprietary networks requires the use of standard con- trol and data signals, the MC68302 can be programmed into the nonmultiplexed serial inter- face (NMSI) mode. This mode, which is available for one, two, or all three SCC ports, can be selected while the other ports use one of the multiplexed interface modes (IDL, GCI, or PCM highway).

References

Last modified on Nov 10, 2018 at 7:03:23 PM Last modified on Nov 10, 2018, 7:03:23 PM