Changes between Version 12 and Version 13 of TBR/BSP/Gen5200


Ignore:
Timestamp:
Nov 10, 2018, 7:01:11 PM (7 months ago)
Author:
Kathryn
Comment:

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  • TBR/BSP/Gen5200

    v12 v13  
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    4 {{Infobox BSP
    5 |image        = TSP3289_IMG_LITE5200.jpg
    6 |BSP_name     = gen5200
    7 |Manufacturer = Multiple
    8 |Board_URL       = http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=Lite5200B
    9 |Architecture = PowerPC
    10 |CPU_model    = Freescale MPC5200
    11 |RAM     = 128 MB DDR SDRAM, 32 MB Flash
    12 |Serial = 2 serial ports
    13 |Aliases      = icecube, pm520_cr285, pm520_ze30, brs51
    14 }}
     4= Infobox BSP =
     5||'''image'''        ||TSP3289_IMG_LITE5200.jpg
     6||'''BSP_name'''     ||gen5200
     7||'''Manufacturer''' ||Multiple
     8||'''Board_URL'''    ||http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=Lite5200B
     9||'''Architecture''' ||PowerPC
     10||'''CPU_model'''    ||Freescale MPC5200
     11||'''RAM'''          ||128 MB DDR SDRAM, 32 MB Flash
     12||'''Serial'''       ||2 serial ports
     13||'''Aliases'''      ||icecube, pm520_cr285, pm520_ze30, brs51
     14
    1515
    1616This BSP supports boards based on the Freescale MPC5200 microcontroller. The following boards are known to work with this BSP:
     
    106106
    107107
    108 {{Test Report
    109 |Version = CVS head
    110 |Date    = 25 March 2011
    111 |User    = [wiki:User:Richard_Campbell User:Richard Campbell]
    112 |Report  = Successfully ran ticker and File I/O test on the Lite5200B in the RTEMS Lab.
    113 }}
     108Test Report
     109||'''Version''' ||CVS head||
     110||'''Date'''    ||25 March 2011||
     111||'''User'''    ||[wiki:User:Richard_Campbell User:Richard Campbell]||
     112||'''Report'''  ||Successfully ran ticker and File I/O test on the Lite5200B in the RTEMS Lab. ||
     113
    114114
    115115CVS Head 2007-06-20: [wiki:TBR/User/JoelSherrill JoelSherrill] reports that he has run most tests successfully on an EP5200C.  Some tmtests exit with an Exception 3 but still report reasonable times.